Patents by Inventor Koichi Masuda

Koichi Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146290
    Abstract: A light source drive circuit according to an embodiment includes: a first delay circuit (10) that gives, based on a clock signal, a delay to an input signal with first time resolution and a second delay circuit (20) that is connected in series to the first delay circuit, gives, based on the clock signal, a delay to an input signal with a second time resolution having accuracy different from accuracy of the first time resolution, and outputs the signal as a signal for driving a light source.
    Type: Application
    Filed: March 2, 2022
    Publication date: May 2, 2024
    Inventors: TAKASHI MASUDA, DAISUKE SUZUKI, MITSUSHI TABATA, KOICHI OKAMOTO, KOUTA HIYAMA
  • Publication number: 20240128282
    Abstract: A semiconductor device (10) according to one aspect of the present disclosure includes: a driving section (40) that drives an object to be driven; an abnormality detecting circuit (30), which is one example of an instruction circuit that outputs an instruction signal to the driving section (40); and a light amount detecting section (20) that detects an amount of incident light and invalidates the instruction signal output from the abnormality detecting circuit (30) in accordance with the amount of incident light.
    Type: Application
    Filed: February 16, 2022
    Publication date: April 18, 2024
    Inventors: Koichi Okamoto, Hideaki Mogi, Takashi Masuda, Shinichirou Saeki, Mitsushi Tabata
  • Publication number: 20240101923
    Abstract: This disclosure describes a zinc-free lubricating oil composition. The composition includes a major amount of an oil of lubricating viscosity having a kinematic viscosity at 100° C. in a range of about 1.5 to about 35 mm2/s and an anti-wear mixture having one or more ashless dispersants and an alkyl phosphonic acid having a structure given by wherein R is a C3-C20 hydrocarbyl group. The initial pH of the anti-wear mixture is between 5-9.5 as measured by ASTM D664.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 28, 2024
    Applicant: CHEVRON JAPAN LTD.
    Inventors: Masami FUCHI, Naoya SASAKI, Takahiro NAKAGAWA, Satoshi OHTA, Naoki MASUDA, Koichi KUBO
  • Patent number: 11936305
    Abstract: An object is to provide a technique capable of improving the power efficiency of a semiconductor device. The semiconductor device includes first to sixth parallel connection bodies, each including a semiconductor switching element and a diode connected in antiparallel to the semiconductor switching element. At least one of the voltage drops of the second parallel connection body and the third parallel connection body is smaller than a voltage drop of at least one of the first parallel connection body, the fourth parallel connection body, the fifth parallel connection body, and the sixth parallel connection body.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: March 19, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koichi Masuda
  • Publication number: 20240075557
    Abstract: A build system includes: a build apparatus including an energy beam irradiation unit, a material supply unit, and a control apparatus. The build system builds a second object above a first object including a first space. The second object includes: a first inclination part connected to the first object; a second inclination part connected to the first object; and a connection part that connects a tip of the first inclination part and a tip of the second inclination part. The build system builds the first inclination part and the second inclination part by alternately performing a building of a part of the first inclination part and a building of a part of the second inclination part. A second space below the first inclination part and the second inclination part is connected to the first space, and an upper part of the second space is closed by the connection part.
    Type: Application
    Filed: January 22, 2021
    Publication date: March 7, 2024
    Applicant: NIKON CORPORATION
    Inventors: Kazuki UENO, Motofusa ISHIKAWA, Koichi YASUBA, Kei SEKIGUCHI, Atsuko MASUDA, Fumika SHIKI
  • Patent number: 11915882
    Abstract: A ceramic electronic device includes a multilayer chip in which a dielectric layer and an internal electrode layer are alternately stacked. Concentration peaks of two or more types of metals different from a main component metal of the internal electrode layer exist at different positions in a stacking direction of the dielectric layer and the internal electrode layer, between the dielectric layer and the internal electrode layer.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Hidetoshi Masuda, Kotaro Mizuno, Koichi Tsukagoshi
  • Patent number: 11894839
    Abstract: According to the present disclosure, a bidirectional switch circuit includes a first semiconductor device including a first backside electrode electrically connected to a first pattern and a first upper surface electrode, a second semiconductor device including a second backside electrode electrically connected to a second pattern and a second upper surface electrode, a first diode including a first cathode electrode electrically connected to the first pattern and a first anode electrode, a second diode including a second cathode electrode electrically connected to the first pattern and a second anode electrode, first wiring electrically connecting the first upper surface electrode and the second anode electrode and second wiring electrically connecting the second upper surface electrode and the first anode electrode, wherein the first upper surface electrode, the second upper surface electrode, the first anode electrode and the second anode electrode are electrically connected to each other.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: February 6, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koichi Masuda, Mituharu Tabata
  • Patent number: 11829754
    Abstract: A vector load instruction generating unit of a compile device generates an instruction to load a “first group of data units”, which is used as an element A[i] in iterative calculation processing, from a memory into a first vector register in a state of being packed in units of 1-word. Each data unit is (1/2)k word. The vector load instruction generating unit generates an instruction to load a second group of data units, which is used as an element [i+2k] into a second vector register. A vector shift double instruction generating unit generates an instruction to cause a part of a data string, which is obtained by shifting data of the first vector Register and the second register by (1/2)k word as a series of data string, to be stored in a third vector register in a state of being packed in units of 1-word.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: November 28, 2023
    Assignee: NEC CORPORATION
    Inventor: Koichi Masuda
  • Patent number: 11635903
    Abstract: A data storage change is received for a piece of data, wherein the data storage change is from a first location to a second location. Two or more possible paths to perform the data storage change are determined. A plurality of weights for each path of the two or more paths is determined. A weighted transfer time for each path of the two or more paths is determined.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: April 25, 2023
    Assignee: International Business Machines Corporation
    Inventors: Koichi Masuda, Shinsuke Mitsuma, Eiji Tosaka, Naoki Imai, Yuki Asakura
  • Patent number: 11630738
    Abstract: A method, computer system, and a computer program product for objective-based compression level change is provided. The present invention may include storing a volume in a storage device, wherein the stored volume is compressed using an initial compression level. The present invention may also include checking a last access time of the stored volume in the storage device at a regular interval. The present invention may further include, in response to determining, based on the checked last access time, that the stored volume is not accessed at the regular interval, recompressing the stored volume in the storage device using a higher compression level, wherein the higher compression level includes a higher compression ratio than a compression ratio associated with the initial compression level.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: April 18, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Koichi Masuda, Kousei Kawamura, Shinsuke Mitsuma, Ryohta Kawase, Eiji Tosaka, Sosuke Matsui
  • Publication number: 20230090703
    Abstract: According to the present disclosure, a bidirectional switch circuit includes a first semiconductor device including a first backside electrode electrically connected to a first pattern and a first upper surface electrode, a second semiconductor device including a second backside electrode electrically connected to a second pattern and a second upper surface electrode, a first diode including a first cathode electrode electrically connected to the first pattern and a first anode electrode, a second diode including a second cathode electrode electrically connected to the first pattern and a second anode electrode, first wiring electrically connecting the first upper surface electrode and the second anode electrode and second wiring electrically connecting the second upper surface electrode and the first anode electrode, wherein the first upper surface electrode, the second upper surface electrode, the first anode electrode and the second anode electrode are electrically connected to each other.
    Type: Application
    Filed: March 24, 2022
    Publication date: March 23, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Koichi MASUDA, Mituharu TABATA
  • Publication number: 20230069350
    Abstract: Provided herein are methods and compositions for long term treatment of spinal pain. In particular, use of double-stranded oligonucleotide decoys capable of binding to the DNA binding sites of two transcription factors are provided for treatment of spinal pain for over seven days, where the decoys are administered without a drug delivery system.
    Type: Application
    Filed: January 14, 2021
    Publication date: March 2, 2023
    Inventors: Koichi Masuda, Takahiro Nakazawa
  • Patent number: 11594464
    Abstract: A semiconductor device includes a semiconductor element, a base plate, and a plurality of contact materials. The base plate has a front surface holding the semiconductor element and a rear surface to which a cooling body to cool the semiconductor element is attachable. The plurality of contact materials are discretely arranged on the rear surface of the base plate. The plurality of contact materials are materials for bridging a gap on a heat dissipation path between the base plate and the cooling body. The plurality of contact materials each have a volume based on a bowed shape of the rear surface of the base plate. From among the plurality of contact materials, a contact material at a concave of the bowed shape has a greater volume than a contact material at a convex of the bowed shape.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: February 28, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Yamashita, Koichi Masuda, Hiroki Muraoka
  • Publication number: 20230034007
    Abstract: Provided herein are systems and methods for preserving and transporting tissues for transplantation. In particular, tissue to be implanted is encapsulated in an alginate gel, which is exposed to culture medium to improve cell viability and suppress inflammatory factors during long-term storage and transport.
    Type: Application
    Filed: January 13, 2021
    Publication date: February 2, 2023
    Inventor: Koichi Masuda
  • Publication number: 20230006571
    Abstract: An object is to provide a technique capable of improving the power efficiency of a semiconductor device. The semiconductor device includes first to sixth parallel connection bodies, each including a semiconductor switching element and a diode connected in antiparallel to the semiconductor switching element. At least one of the voltage drops of the second parallel connection body and the third parallel connection body is smaller than a voltage drop of at least one of the first parallel connection body, the fourth parallel connection body, the fifth parallel connection body, and the sixth parallel connection body.
    Type: Application
    Filed: March 7, 2022
    Publication date: January 5, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventor: Koichi MASUDA
  • Publication number: 20220398027
    Abstract: A data storage change is received for a piece of data, wherein the data storage change is from a first location to a second location. Two or more possible paths to perform the data storage change are determined. A plurality of weights for each path of the two or more paths is determined. A weighted transfer time for each path of the two or more paths is determined.
    Type: Application
    Filed: June 15, 2021
    Publication date: December 15, 2022
    Inventors: Koichi Masuda, Shinsuke Mitsuma, Eiji Tosaka, Naoki Imai, YUKI ASAKURA
  • Patent number: 11487430
    Abstract: Embodiments are provided for reducing data using a plurality of compression operations in a computing storage environment. A speed of data writing to a virtual tape device and an availability of one or more processor devices for the virtual tape device may be monitored. One or more requests may be received for writing data to the virtual tape device. Data to be written to the virtual tape device, corresponding to a selected number of the one or more requests for writing the data, may be compressed according to both the speed of data writing to the virtual tape device and the availability of one or more processor devices for the virtual tape device. The compressed data may be stored in the virtual tape device in record units. Non-compressed data may be compressed in the virtual tape device at a subsequent period of time (e.g., future time period).
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: November 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takahiro Tsuda, Koichi Masuda, Sosuke Matsui, Takeshi Nohta, Shinsuke Mitsuma, Kousei Kawamura
  • Patent number: 11442627
    Abstract: An embodiment of the invention may include a method, computer program product and system for saving data received from a host computing device to a storage system. The storage system includes at least one processor and at least one storage. An embodiment may include storing the received data to the storage on a record basis. A record includes a record header including information indicative of an implemented compression method of the record. An embodiment may include monitoring a processing load of the at least one processor. In response to the processing load being less than a predetermined level, an embodiment may include further compressing the record utilizing a high-ratio compression method based on the record requiring further compression. An embodiment may include updating the record header information to reflect details of the utilized a high-ratio compression method. An embodiment may include storing the further compressed record to the storage.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: September 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Ryohta Kawase, Eiji Tosaka, Kousei Kawamura, Koichi Masuda, Shinsuke Mitsuma
  • Publication number: 20220072026
    Abstract: Provided herein are methods and compositions for treating spinal conditions. In particular, use of double-stranded oligonucleotide decoys capable of binding to the DNA binding sites of two transcription factors (NF-?B and STAT6) for treatment of intervertebral disc degeneration, regenerating a chondrocyte extracellular matrix, spinal pain, and promoting synthesis of proteoglycan in intervertebral disc cells.
    Type: Application
    Filed: December 24, 2019
    Publication date: March 10, 2022
    Inventors: Koichi MASUDA, Takahiro NAKAZAWA
  • Publication number: 20220027151
    Abstract: A vector load instruction generating unit (12) of a compile device (10) generates an instruction to load a “first group of data units”, which is used as an element a[i] in iterative calculation processing, from a memory into a first vector register in a state of being packed in units of 1-word. Each data unit is (1/2)k word. The vector load instruction generating unit (12) generates an instruction to load a second group of data units, which is used as an element [i+2k] into a second vector register. A vector shift double instruction generating unit (13) generates an instruction to cause a part of a data string, which is obtained by shifting data of the first vector register and the second register by (1/2)k word as a series of data string, to be stored in a third vector register in a state of being packed in units of 1-word.
    Type: Application
    Filed: October 11, 2019
    Publication date: January 27, 2022
    Applicant: NEC Corporation
    Inventor: Koichi MASUDA