Patents by Inventor Koichi Matsumoto

Koichi Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220146965
    Abstract: An endless belt includes: a resin; and electrically conductive particles, wherein an integrated discharge amount is 350 ?C or less. The integrated discharge amount is determined by disposing an electrode at a position spaced 60 ?m apart from the outer circumferential surface of the belt, applying a voltage to the electrode, and measuring the amount of discharge for a period of 1 second after the voltage reaches 1300 V.
    Type: Application
    Filed: May 5, 2021
    Publication date: May 12, 2022
    Applicant: FUJIFILM Business Innovation Corp.
    Inventors: Daisuke TANEMURA, Shigeru FUKUDA, Satoya SUGIURA, Tomotake INAGAKI, Masato ONO, Masato FURUKAWA, Hiroaki TANAKA, Kenta YAMAKOSHI, Ryohei YOSHIKAWA, Yosuke KUBO, Masayuki SEKO, Koichi MATSUMOTO
  • Publication number: 20220020879
    Abstract: Noise in a semiconductor device is to be reduced. The semiconductor device includes a first semiconductor region, a gate electrode, and a second semiconductor region. In the first semiconductor region, a source region, a channel formation region, and a drain region that are of the same conductivity type are provided. The gate electrode is disposed adjacent to the channel formation region via an insulating film disposed on a surface of the first semiconductor region. The second semiconductor region is disposed adjacent to the channel formation region on a different surface from the surface on which the gate electrode is disposed, and forms a depletion layer in the channel formation region.
    Type: Application
    Filed: November 28, 2019
    Publication date: January 20, 2022
    Inventor: KOICHI MATSUMOTO
  • Publication number: 20210391366
    Abstract: A semiconductor device according to an aspect of the present technology includes a low-concentration N-type region, a first high-concentration N-type region and a second high-concentration N-type region that are stacked with the low-concentration N-type region interposed therein, a gate electrode that surrounds the low-concentration N-type region as viewed from a stacking direction, which is a direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked, a first insulating film placed between the gate electrode and the low-concentration N-type region, and a second insulating film placed between the gate electrode and the first high-concentration N-type region. The first high-concentration N-type region is connected to one of a source electrode and a drain electrode. The second high-concentration N-type region is connected to the other of the source electrode and the drain electrode.
    Type: Application
    Filed: October 2, 2019
    Publication date: December 16, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Katsuhiko FUKASAKU, Koichi MATSUMOTO, Akito SHIMIZU
  • Publication number: 20210375865
    Abstract: A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.
    Type: Application
    Filed: August 11, 2021
    Publication date: December 2, 2021
    Applicant: Sony Corporation
    Inventor: Koichi Matsumoto
  • Patent number: 11121133
    Abstract: A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: September 14, 2021
    Assignee: SONY CORPORATION
    Inventor: Koichi Matsumoto
  • Publication number: 20210242204
    Abstract: Disclosed herein is a composite transistor which includes a first transistor TR1 including a control electrode, a first active region, a first A extending part, and a first B extending part, and a second transistor TR2 including a control electrode, a second active region, a second A extending part, and a second B extending part. The first active region, the second active region, and the control electrode overlap one another. Both the first A extending part and the first B extending part extend from the first active region and both the second A extending part and the second B extending part extend from the second active region. The first electrode is connected to the first A extending part, the second electrode is connected to the second A extending part, and the third electrode is connected to the first B extending part and the second B extending part.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Applicant: SONY GROUP CORPORATION
    Inventor: Koichi MATSUMOTO
  • Patent number: 11081550
    Abstract: A tunnel field-effect transistor has a stacked structure including a second active region, a first active region, and a control electrode. The first active region includes a first-A active region and a first-B active region between the first-A active region and a first active region extension portion. A second active region exists below the first-A active region, and the second active region does not exist below the first-B active region. Where an orthographic projection image of the second active region and an orthographic projection image of the first active region overlap with each other is defined as L2-Total, and a length in a Y direction of the first active region is defined as L1-Y, when an axial direction of the first active region is defined as an X direction, and a stacked direction of the stacked structure is defined as a Z direction, L1-Y<L2-Total is satisfied.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: August 3, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Koichi Matsumoto
  • Publication number: 20210225841
    Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211,212 respectively.
    Type: Application
    Filed: April 7, 2021
    Publication date: July 22, 2021
    Inventors: Hidetoshi OISHI, Koichi MATSUMOTO, Kazuyuki TOMIDA
  • Patent number: 11004848
    Abstract: Disclosed herein is a composite transistor which includes a first transistor TR1 including a control electrode, a first active region, a first A extending part, and a first B extending part, and a second transistor TR2 including a control electrode, a second active region, a second A extending part, and a second B extending part. The first active region, the second active region, and the control electrode overlap one another. Both the first A extending part and the first B extending part extend from the first active region and both the second A extending part and the second B extending part extend from the second active region. The first electrode is connected to the first A extending part, the second electrode is connected to the second A extending part, and the third electrode is connected to the first B extending part and the second B extending part.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: May 11, 2021
    Assignee: SONY CORPORATION
    Inventor: Koichi Matsumoto
  • Patent number: 11004851
    Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211, 212 respectively.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 11, 2021
    Assignee: SONY CORPORATION
    Inventors: Hidetoshi Oishi, Koichi Matsumoto, Kazuyuki Tomida
  • Patent number: 10996594
    Abstract: An endless belt includes either a single-layer body including a layer including an imide resin and conductive particles, or a multilayer body including the layer as an outermost layer. The ratio y/x of the layer is 0.8992 or more and 1.0157 or less, where x [log ?/?] is the common logarithm of the surface resistivity of the outer peripheral surface of the layer measured with a ring probe when a voltage of 100 V is applied to the layer for 3 seconds at a load of 1 kg, and y [log ?·cm] is the common logarithm of the volume resistivity of the layer measured with a ring probe when a voltage of 100 V is applied to the layer for 5 seconds at a load of 1 kg.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: May 4, 2021
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Hiroaki Tanaka, Satoya Sugiura, Daisuke Tanemura, Masato Ono, Masato Furukawa, Shigeru Fukuda, Masayuki Seko, Koichi Matsumoto, Shogo Hayashi, Tomoko Suzuki
  • Patent number: 10976690
    Abstract: Provided is a transfer device that includes an intermediate transfer body which is a first endless belt including a resin and conductive carbon particles and in which in a spatial distribution of the conductive carbon particles that are present in an evaluation region of 6.3 ?m×4.2 ?m on an outer peripheral surface; a first transfer component that first-transfers a toner image formed on a surface of an image carrier to a surface of the intermediate transfer body; and a second transfer component which has a second endless belt disposed so as to face the outer peripheral surface of the intermediate transfer body, which second-transfers the toner image transferred to the surface of the intermediate transfer body to a surface of a recording medium on the second endless belt.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 13, 2021
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Masato Furukawa, Shigeru Fukuda, Futoshi Takei, Satoya Sugiura, Daisuke Tanemura, Masato Ono, Hiroaki Tanaka, Shogo Hayashi, Minoru Rokutan, Tomoko Suzuki, Masayuki Seko, Koichi Matsumoto
  • Patent number: 10935908
    Abstract: A transfer unit includes an intermediate transfer belt including a resin and in which in a spatial distribution of conductive carbon particles that are present in an evaluation region of 6.3 ?m×4.2 ?m on an outer peripheral surface, an integrated value of a statistic L(r) in an interparticle distance r of 0.05 ?m or more and 0.30 ?m or less is 0 or more and 0.1 or less; and a cleaning component including a cleaning blade which contacts the outer peripheral surface of the intermediate transfer belt and in which a value of M100/Re is 0.25 or more and a value of Re is 25 or more where M100 represents a 100% modulus (MPa) of a contact portion of the cleaning blade contacts the intermediate transfer belt, and Re represents a rebound resilience coefficient (%) of the contact portion: L(r):=?{square root over (K(r)/?)}?r??(1) K ? ( r ) := ? i ? j N ? 1 ? ( ? X i - X j ? ? r ) / s ? ( ? X i - X j ? ) ? 2 .
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 2, 2021
    Assignee: FUJI XEROX CO.. LTD.
    Inventors: Masayuki Seko, Shigeru Fukuda, Satoya Sugiura, Daisuke Tanemura, Masato Ono, Masato Furukawa, Hiroaki Tanaka, Shogo Hayashi, Koichi Matsumoto, Daisuke Tano
  • Publication number: 20210005607
    Abstract: A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Applicant: Sony Corporation
    Inventor: Koichi Matsumoto
  • Patent number: 10831133
    Abstract: An endless belt includes a first resin and first conductive carbon particles. In the spatial distribution of the first conductive carbon particles present in an evaluation region of the outer peripheral surface of the endless belt which has a size of 6.3 ?m×4.2 ?m, the integral of the statistic L(r) represented by Formula (1) below from 0.05 ?m to 0.30 ?m with respect to an interparticle distance r is 0 or more and 0.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: November 10, 2020
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Satoya Sugiura, Shigeru Fukuda, Futoshi Takei, Daisuke Tanemura, Masato Ono, Masato Furukawa, Hiroaki Tanaka, Shogo Hayashi, Tomoko Suzuki, Masayuki Seko, Koichi Matsumoto, Minoru Rokutan
  • Patent number: 10811416
    Abstract: A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: October 20, 2020
    Assignee: SONY CORPORATION
    Inventor: Koichi Matsumoto
  • Patent number: D938629
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: December 14, 2021
    Inventors: Tomonori Matsumoto, Kazuhiko Ito, Koichi Matsumoto
  • Patent number: D940018
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: January 4, 2022
    Inventors: Tomonori Matsumoto, Kosuke Kubo, Koichi Matsumoto
  • Patent number: D940019
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: January 4, 2022
    Inventors: Kosuke Kubo, Koichi Matsumoto, Kazuhiko Ito
  • Patent number: D940361
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: January 4, 2022
    Inventors: Kazuhiko Ito, Koichi Matsumoto, Atsushi Kochi, Kazuki Aiba, Kohei Kobayashi