Patents by Inventor Koichi Matsuno

Koichi Matsuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250252998
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers including stepped surfaces, a dielectric material portion overlying the stepped surfaces of the alternating stack, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, and a dielectric support assembly. The dielectric support assembly includes a plurality of dielectric pillar structures and a dielectric connection plate. The plurality of dielectric pillar structures vertically extend through the stepped surfaces, the dielectric material portion, and an underlying portion of the alternating stack. The dielectric connection plate overlies the stepped surfaces and contacts and laterally surrounds each of the plurality of dielectric pillar structures.
    Type: Application
    Filed: February 5, 2024
    Publication date: August 7, 2025
    Inventors: Koichi MATSUNO, Ruogu Matthew ZHU, Johann ALSMEIER
  • Patent number: 12322710
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory opening fill structures including a respective vertical semiconductor channel and a respective memory film, and support pillar structures including a respective dummy vertical semiconductor channel, a respective dummy memory film, and a vertical stack of dielectric spacer fins located at levels of the electrically conductive layers and interposed between the electrically conductive layers and the respective dummy memory film.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: June 3, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Jixin Yu, Johann Alsmeier, Koichi Matsuno
  • Patent number: 12288755
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a dielectric moat fill structure that includes a nested structure including, from outside to inside, an outer dielectric liner having a first Young's modulus, an outer material layer having a second Young's modulus greater than the first Young's modulus, a dielectric fill material portion, an inner material layer having the second Young's modulus, and an inner dielectric liner having the first Young's modulus, a vertically alternating sequence of insulating plates and dielectric material plates at least partially laterally surrounded by the dielectric moat fill structure, and an interconnection via structure vertically extending the vertically alternating sequence.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: April 29, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventor: Koichi Matsuno
  • Publication number: 20250133737
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers, forming memory openings through the alternating stack, forming memory opening fill structures in the memory openings, forming a first support opening and a second support opening through the alternating stack, laterally expanding the first support opening without expanding the second support opening, forming a first dielectric support pillar structure and a second dielectric support pillar structure in the laterally-expanded first support opening and in the second support opening, respectively, and replacing the sacrificial material layers with electrically conductive layers. Each of the memory opening fill structures includes vertical semiconductor channel and a respective vertical stack of memory elements.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 24, 2025
    Inventors: Tomohiro KUBO, Koichi MATSUNO
  • Publication number: 20250126784
    Abstract: A three-dimensional memory device includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers each of which includes a horizontally-extending portion and a slanted portion that extends at a non-zero and non-orthogonal angle relative to the horizontally-extending portion, where each slanted portion has a horizontal end surface located within a first horizontal plane, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and layer contact via structures having a respective end surface that contacts a respective one of the end surfaces of the slanted portions of the electrically conductive layers within the first horizontal plane.
    Type: Application
    Filed: October 17, 2023
    Publication date: April 17, 2025
    Inventors: Johann ALSMEIER, Senaka KANAKAMEDALA, Akira YOSHIDA, James KAI, Koichi MATSUNO, Mark D. KRAMAN
  • Patent number: 12255242
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: March 18, 2025
    Assignee: Sandisk Technologies Inc.
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Koichi Matsuno
  • Publication number: 20250081453
    Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers, where each of the alternating stacks laterally extends along a first horizontal direction, and the alternating stacks are laterally spaced apart from each other along a second horizontal direction by lateral isolation trenches, arrays of memory openings, where each array of memory openings vertically extends through a respective one of the alternating stacks, arrays of memory opening fill structures located within the arrays of memory openings, where each of the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel, and composite lateral isolation trench fill structures located between a respective neighboring pair of the alternating stacks.
    Type: Application
    Filed: April 25, 2024
    Publication date: March 6, 2025
    Inventors: Yuya SANADA, Koichi MATSUNO, Tomohiro KUBO, Johann ALSMEIER
  • Publication number: 20250079294
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in memory opening and including a vertical stack of memory elements located at levels of the electrically conductive layers and a vertical semiconductor channel, a layer contact via structure contacting a first electrically conductive layer within a first subset of the electrically conductive layers and vertically extending through a second subset of the electrically conductive layers that overlies the first subset, and a support pillar structure located under a bottom surface of the layer contact via structure.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 6, 2025
    Inventors: Jixin YU, Koichi MATSUNO, Ruogu Matthew ZHU, Mark D. KRAMAN, Johann ALSMEIER
  • Publication number: 20250081458
    Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers laterally extending along a first horizontal direction and laterally spaced apart along a second horizontal direction by lateral isolation trenches, arrays of memory openings vertically extending through the alternating stacks, arrays of memory opening fill structures located within the arrays of memory openings and including a respective vertical stack of memory elements and a vertical semiconductor channel, and composite lateral isolation trench fill structures located between a respective neighboring pair of the alternating stacks. Each of the composite lateral isolation trench fill structures includes a dielectric pillar structure which vertically extends at least from first horizontal plane including a bottom of the alternating stacks to a second horizontal plane including a top of the alternating stacks.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 6, 2025
    Inventors: Koichi MATSUNO, Tomohiro KUBO, Johann ALSMEIER
  • Patent number: 12243865
    Abstract: A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: March 4, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Johann Alsmeier, James Kai, Koichi Matsuno
  • Publication number: 20250014990
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through each layer within the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements a vertical semiconductor channel, and a contact via structure. The contact via structure includes a conductive pillar portion vertically extending at least from a first horizontal plane including a bottommost surface of the alternating stack to a second horizontal plane including a topmost surface of the alternating stack, and an annular conductive fin portion laterally protruding from the conductive pillar portion and contacting one of the electrically conductive layers. A vertical stack of annular insulating plates laterally surrounds the conductive pillar portion and underlies the conductive fin portion.
    Type: Application
    Filed: August 12, 2024
    Publication date: January 9, 2025
    Inventors: Tomohiro KUBO, Koichi MATSUNO
  • Publication number: 20240414917
    Abstract: A memory device includes a first alternating stack including first insulating layers and first electrically conductive layers that are interlaced along a vertical direction, where a first stepped cavity located inside the first alternating stack includes a first stepped bottom surface containing horizontally-extending surface segments of the first electrically conductive layers, a memory opening vertically extending through each layer within the first alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements, a first insulating spacer contacting sidewalls of the first stepped cavity, and a first electrically conductive strip including a first horizontally-extending bottom strip segment contacting one of the first electrically conductive layers, a first horizontally-extending top strip segment that overlies a topmost layer within the first alternating stack, and a first vertically-extending strip segment connecting the first horizontally-
    Type: Application
    Filed: September 7, 2023
    Publication date: December 12, 2024
    Inventors: Mark D. KRAMAN, Ruogu Matthew ZHU, Li-Wei LO, Koichi MATSUNO, Jixin YU, Kazuhiro SHIRAISHI, Takayuki MAEKURA
  • Publication number: 20240395710
    Abstract: A semiconductor structure includes alternating stacks of insulating layers and electrically conductive layers which are located over a substrate and are laterally spaced apart among one another by first backside trenches and second backside trenches that are interlaced along a horizontal direction, first backside trench fill structures located in the first backside trenches, and second backside trench fill structures located in the second backside trenches. Each of the first backside trench fill structures includes a respective set of first backside bridge support structures comprising a first material, and each of the second backside trench fill structures includes a respective set of second backside bridge support structures comprising a second material that is different from the first material.
    Type: Application
    Filed: August 8, 2024
    Publication date: November 28, 2024
    Inventors: Koichi MATSUNO, Tomohiro KUBO, Johann ALSMEIER
  • Publication number: 20240386959
    Abstract: A three-dimensional memory device includes at least one alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the at least one alternating stack, memory opening fill structures located in the memory openings, and a laterally-extending trench fill structure contacting a first lengthwise sidewall of the at least one alternating stack, and including a first-type dielectric bridge structure having a first volume, a second-type dielectric bridge structure having a second volume greater than the first volume, and a trench dielectric material portion.
    Type: Application
    Filed: August 15, 2023
    Publication date: November 21, 2024
    Inventors: Jixin YU, Koichi MATSUNO, Seyyed Ehsan Esfahani RASHIDI, Ehsan ESMAILI, Johann ALSMEIER
  • Patent number: 12148710
    Abstract: A three-dimensional memory device includes a first alternating stack of first word lines and first insulating layers, first memory stack structures vertically extending through the first alternating stack, a second alternating stack of second word lines and second insulating layers, second memory stack structures vertically extending through the second alternating stack, plural backside trench fill structures located between the first alternating stack and the second alternating stack, and a bridge region located between the plural backside trench fill structures and between the between the first alternating stack and the second alternating stack. At least one insulating layer extends continuously through the first alternating stack, the second alternating stack, and the bridge region.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: November 19, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Koichi Matsuno, Johann Alsmeier
  • Publication number: 20240373631
    Abstract: A memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first dielectric material portion overlying first stepped surfaces of the first alternating stack, a memory opening vertically extending through the first alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of memory elements, and a first contact via structure vertically extending through the first alternating stack and the first dielectric material portion. The first contact via structure includes a conductive pillar portion and a conductive fin portion that laterally protrudes from the conductive pillar portion and having a first annular bottom surface segment contacting an annular top surface segment of one of the first electrically conductive layers.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 7, 2024
    Inventors: Koichi MATSUNO, Johann ALSMEIER
  • Publication number: 20240373633
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers containing stepped surfaces in a contact region, a first stepped dielectric material portion overlying the stepped surfaces of the alternating stack, a memory opening vertically extending at least through each layer within the alternating stack, a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel, and a bundled contact via structure vertically extending through the first stepped dielectric material portion and through a plurality of bottommost electrically conductive layers of the electrically conductive layers, and laterally contacting each of the plurality of the bottommost electrically conductive layers.
    Type: Application
    Filed: August 25, 2023
    Publication date: November 7, 2024
    Inventors: Mohan DUNGA, Koichi MATSUNO
  • Publication number: 20240371789
    Abstract: A memory device includes layer stacks, each including a respective alternating stack of respective insulating layers and respective electrically conductive layers and a respective contact-level dielectric layer, memory openings vertically extending through a respective one of the alternating stacks. memory opening fill structures located in a respective one of the memory openings and including a respective vertical stack of memory elements and a respective vertical semiconductor channel, and dielectric bridges structures located within access trenches that laterally separate the layer stacks. Each of the dielectric bridge structures includes a respective pair of contoured sidewalls. Each contoured sidewall of the dielectric bridge structures includes at least two vertically-straight and horizontally-convex surface segments that are adjoined by a vertically-extending edge.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 7, 2024
    Inventors: Koichi MATSUNO, Johann ALSMEIER
  • Patent number: 12133388
    Abstract: A memory device includes a lower source-level semiconductor layer, a source contact layer, an upper source-level semiconductor layer, and an alternating stack of insulating layers and electrically conductive layers, and a memory opening fill structure vertically extending through the alternating stack and down to an upper portion of the lower source-level semiconductor layer. The memory opening fill structure includes a vertical semiconductor channel, a memory film laterally surrounding the vertical semiconductor channel, and an annular semiconductor cap contacting a bottom surface of the memory film and contacting a top surface segment of the source contact layer. The annular semiconductor cap may be employed as an etch stop structure during a manufacturing process.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: October 29, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kota Funayama, Satoshi Shimizu, Koichi Matsuno
  • Publication number: 20240334695
    Abstract: A three-dimensional memory device includes laterally spaced apart vertical stacks of electrically conductive layers and insulating layers. A composite dielectric isolation structure provides electrical isolation between neighboring pairs of vertical stacks. The composite dielectric isolation structure includes at least one retro-stepped dielectric material portion, and may further include at least one finned insulating support structure or a vertical stack of dielectric material plates.
    Type: Application
    Filed: July 27, 2023
    Publication date: October 3, 2024
    Inventors: Jixin YU, Koichi MATSUNO, Ruogu Matthew ZHU, Johann ALSMEIER