Abstract: A semiconductor structure includes a semiconductor device, bit lines electrically connected to the semiconductor device, air gaps located between the bit lines, a capping-level material layer, a via-level dielectric material layer located between the bit lines and the capping-level material layer, and conductive via structures extending through the via-level dielectric material layer and contacting a top surface of a respective one of the bit lines. The capping-level material layer contains cavity-containing openings exposing the air gaps. The capping-level material layer contains protruding portions that extend into peripheral regions of the cavity-containing openings.

Abstract: A three-dimensional memory device includes layer stacks located over a substrate and laterally spaced apart from each other by backside trenches. Each of the layer stacks includes a respective alternating stack of insulating layers and electrically conductive layers. Memory openings vertically extend through a respective one of the alternating stacks and are filled with a respective memory opening fill structure. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each backside trench fill structure includes a respective row of backside trench bridge structures that are more distal from the substrate than a most distal one of the electrically conductive layers is from the substrate. The backside trench bridge structures can provide structural support during a replacement process that forms the electrically conductive layers.

Abstract: The present invention relates to an information processing device configured to perform a process of creating, on the basis of original content, at least a first content having a data size smaller than a data size of the original content and a second content having a data size smaller than the data size of the first content, and a process of transferring the original content, the first content, and/or the second content.

Abstract: A three-dimensional memory device includes layer stacks located over a substrate and laterally spaced apart from each other by backside trenches. Each of the layer stacks includes a respective alternating stack of insulating layers and electrically conductive layers. Memory openings vertically extend through a respective one of the alternating stacks and are filled with a respective memory opening fill structure. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each backside trench fill structure includes a respective row of backside trench bridge structures that are more distal from the substrate than a most distal one of the electrically conductive layers is from the substrate. The backside trench bridge structures can provide structural support during a replacement process that forms the electrically conductive layers.

Abstract: A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.

Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.

Abstract: A display device for a musical instrument includes a touch panel and a switcher. The touch panel is placed to be adjacent to an exterior member that constitutes appearance of the musical instrument. The switcher switches appearance of the touch panel between a first mode and a second mode in which the appearance of the touch panel is closer to appearance of the exterior member than in the first mode.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a vertical stack of memory elements, a dielectric moat structure vertically extending through the alternating stack and including an annular dielectric plate portion at each level of the electrically conductive layers that laterally surrounds a respective dielectric material plate, and an interconnection via structure laterally surrounded by the dielectric moat structure and vertically extending through each insulating layer within the alternating stack.

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.

Abstract: An electronic musical instrument includes a condition determiner that determines whether an OFF condition for turning off a power supply is satisfied in an automatic power-OFF mode; a noise gate that is opened when a level of an input audio signal exceeds a threshold value and is closed when the level of the input audio signal continues being equal to or lower than the threshold value for a first predetermined period of time; and a controller that turns off the power supply on the condition that the condition determiner determines that the OFF condition is satisfied in the automatic power-OFF mode; and the controller does not turn off the power supply when the noise gate is in an open state, even in the case where the OFF condition is satisfied.

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.

Abstract: The present invention relates to an information processing device configured to perform a process of creating, on the basis of original content, at least a first content having a data size smaller than a data size of the original content and a second content having a data size smaller than the data size of the first content, and a process of transferring the original content, the first content, and/or the second content.

Abstract: [Object] To provide a technology in which it is possible to improve the communication performance of a communication apparatus. [Solving Means] A booster antenna structure according to the present technology includes: a booster antenna magnetically coupled to an antenna coil of a coil substrate disposed inside a housing of a communication apparatus; and a first magnetic material sheet, the booster antenna structure being disposed at a position on an outer side relative to the coil substrate in the inside of the housing, and having a size larger than that of the coil substrate.

Abstract: An electronic musical instrument includes a condition determiner that determines whether an OFF condition for turning off a power supply is satisfied in an automatic power-OFF mode; a noise gate that is opened when a level of an input audio signal exceeds a threshold value and is closed when the level of the input audio signal continues being equal to or lower than the threshold value for a first predetermined period of time; and a controller that turns off the power supply on the condition that the condition determiner determines that the OFF condition is satisfied in the automatic power-OFF mode; and the controller does not turn off the power supply when the noise gate is in an open state, even in the case where the OFF condition is satisfied.

Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a columnar portion, a hole, and a sealing film. The stacked body includes a plurality of conductive layers stacked with an air gap interposed. The columnar portion includes a semiconductor body. The semiconductor body extends in a stacking direction of the stacked body through the stacked body and contacts the foundation layer. The hole extends in the stacking direction through the stacked body and forms a cavity communicating with the air gap. The sealing film plugs an upper end of the hole forming the cavity.

Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a columnar portion, a hole, and a sealing film. The stacked body includes a plurality of conductive layers stacked with an air gap interposed. The columnar portion includes a semiconductor body. The semiconductor body extends in a stacking direction of the stacked body through the stacked body and contacts the foundation layer. The hole extends in the stacking direction through the stacked body and forms a cavity communicating with the air gap. The sealing film plugs an upper end of the hole forming the cavity.

Abstract: A semiconductor memory device includes a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, and first and second interconnections on a first surface of the stacked body. The first and second electrode layers have first and second end surfaces respectively in the first surface. The first interconnection is electrically connected to the first electrode layer through a first region of the first end surface; and the second interconnection is electrically connected to the second electrode layer through a second region of the second end surface. The first and second interconnections extend in a first direction on the first surface. The first and second regions are arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees. The first region and the second region each have a boundary along the second direction.

Abstract: A semiconductor memory device includes a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, and first and second interconnections on a first surface of the stacked body. The first and second electrode layers have first and second end surfaces respectively in the first surface. The first interconnection is electrically connected to the first electrode layer through a first region of the first end surface; and the second interconnection is electrically connected to the second electrode layer through a second region of the second end surface. The first and second interconnections extend in a first direction on the first surface. The first and second regions are arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees. The first region and the second region each have a boundary along the second direction.