Abstract: A reservoir calculation device according to an embodiment includes a reservoir circuit and an output circuit. The reservoir circuit receives input data and outputs intermediate signals, each undergoing a transient change when the input data changes. The output circuit outputs an output signal obtained by combining the intermediate signals. The reservoir circuit includes intermediate circuits, each including a neuron circuit and an intermediate output circuit. The neuron circuit generates an intermediate voltage undergoing a transient change corresponding to weight data and the input data when the input data changes. The intermediate output circuit outputs an intermediate signal representing a level of the intermediate voltage from the neuron circuit. The neuron circuit includes a time constant circuit capable of changing a time constant. The time constant circuit is connected between a reference potential and an intermediate terminal outputting the intermediate voltage.

Abstract: According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.

Abstract: In a gate electrode of a nonvolatile memory device of an embodiment, a tunnel insulating film covers a channel region. A first current collector file is disposed on the side opposite to the channel region with respect to the tunnel insulating film. An ion conductor film is disposed between the tunnel insulating film and the first current collector film. A first electrode film is disposed between the tunnel insulating film and the ion conductor film. The first electrode film is in contact with the ion conductor film. A second electrode film is disposed between the ion conductor film and the first current collector film. The second electrode film is in contact with the ion conductor film. A second current collector film is disposed between the tunnel insulating film and the second electrode film.

Abstract: A multiplication device according to one embodiment includes a short-term memory circuit, a long-term memory circuit, a conversion circuit, and a control circuit. The short-term memory circuit generates a first control voltage in accordance with a weight value. The long-term memory circuit generates a second control voltage by a circuit with a larger time constant than the short-term memory circuit. The conversion circuit outputs an output current by multiplying an input voltage by a conductance. The output current is output by that, the first control voltage is applied to a control terminal of the conversion circuit, and an input voltage according to an input value is applied to an input terminal of the conversion circuit. The control circuit executes a calibration process of matching the first control voltage with the second control voltage by transferring an electric charge from the long-term memory circuit to the short-term memory circuit.

Abstract: According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.

Abstract: A neural network apparatus according to an embodiment includes neuron circuits, synaptic circuits, and a control circuit. A firing circuit of each neuron circuit outputs a firing signal when absolute value of the internal potential is larger than a firing threshold. A firing threshold adjustment circuit of each neuron circuit changes the firing threshold in accordance with frequency of the firing signal. When the firing signal is output from a pre-synaptic neuron circuit, the synaptic circuit changes the synaptic weight in accordance with a contrast between a learning threshold and the absolute value of the internal potential held in a post-synaptic neuron circuit. The control circuit changes the learning threshold in accordance with frequency of the firing signal from a target neuron circuit. The learning threshold is used for changing the synaptic weight stored in one or more synaptic circuits each outputting the output signal to the target neuron.

Abstract: A variable resistance element according to an embodiment serves to change to a low resistance state or a high resistance state. The variable resistance element includes a first transition metal compound layer, a second transition metal compound layer, and a lithium ion conductor layer. The first transition metal compound layer is connected to a first electrode. The first transition metal compound layer is a metal compound containing lithium ions in lattice interstices. The second transition metal compound layer is connected to a second electrode. The second transition metal compound layer is a metal compound containing lithium ions in lattice interstices. The lithium ion conductor layer is provided between the first transition metal compound layer and the second transition metal compound layer. The lithium ion conductor layer is a solid substance that is permeable to lithium ions and is less permeable to electrons.

Abstract: According to one embodiment, an arithmetic device includes an arithmetic circuit. The arithmetic circuit includes a memory part including a plurality of memory regions, and an arithmetic part. One of the memory regions includes a capacitance including a first terminal, and a first electrical circuit electrically connected to the first terminal and configured to output a voltage signal corresponding to a potential of the first terminal.

Abstract: A synaptic circuit according to an embodiment includes a weight storage circuit and a transmission circuit. The weight storage circuit stores a synaptic weight indicating a first value or a second value. The transmission circuit receives a firing signal output from a pre-synaptic neuron circuit, and supplies an output signal to a post-synaptic neuron circuit. The output signal is obtained by adding, to the firing signal, influence of the synaptic weight. The post-synaptic neuron circuit holds an internal potential. When the firing signal is received, the weight storage circuit causes the synaptic weight to change to indicate the first or second value with a first probability in accordance with a comparison result between the internal potential and a set potential. The weight storage circuit causes the synaptic weight to change to indicate the first value with a second probability regardless of whether or not the firing signal is received.

Abstract: According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.

Abstract: According to an embodiment, an arithmetic device includes a comparator, M cross switches, and M coefficient circuits. The comparator compares a first voltage generated at a first comparison terminal and a second voltage generated at a second comparison terminal. The M cross switches are provided corresponding to the M input signals. The M coefficient circuits are provided corresponding to the M coefficients, and each includes a first constant current source and a second constant current source. Each of the M cross switches performs switching between a straight state and a reverse state. In each of the M coefficient circuits, the first constant current source is connected between a positive output terminal of the corresponding coefficient circuit and a reference potential, and the second constant current source is connected between a negative output terminal of the corresponding coefficient circuit and the reference potential.

Abstract: A memory device according to an embodiment can be used for storing weights for a neural network. An update circuit changes a difference between charge amounts accumulated in first/second accumulation circuits in the memory device. An output circuit outputs, as a weight, a signal corresponding to the difference between the charge amounts. The update circuit performs the change of the difference by changing, when the update amount is positive, the electric charges accumulated in the first accumulation circuit in a first direction by a charge amount corresponding to an absolute value of the update amount, the first direction being either an increasing direction or a decreasing direction, and changing, when the update amount is negative, the electric charges accumulated in the second accumulation circuit in the first direction by a charge amount corresponding to an absolute value of the update amount.

Abstract: In a gate electrode of a nonvolatile memory device of an embodiment, a tunnel insulating film covers a channel region. A first current collector file is disposed on the side opposite to the channel region with respect to the tunnel insulating film. An ion conductor film is disposed between. the tunnel insulating film and the first current collector film. A first electrode film is disposed between the tunnel insulating film and the ion conductor film. The first electrode film is in contact with the ion conductor film. A second electrode film. is disposed between the ion conductor film and the first current collector film. The second electrode film is in contact with the ion conductor film. A second current collector film is disposed between the tunnel insulating. film and the second electrode film.

Abstract: A synaptic circuit according to an embodiment is a circuit in which a weight value changed by learning is set. The synaptic circuit receives a binary input signal from a pre-synaptic neuron circuit and outputs an output signal to a post-synaptic neuron circuit. The synaptic circuit includes a propagation circuit and a control circuit. The propagation circuit supplies, to the post-synaptic neuron circuit, the output signal obtained by adding an influence of the weight value to the input signal. The control circuit stops output of the output signal from the propagation circuit to the post-synaptic neuron circuit when the weight value is smaller than a predetermined reference value.

Abstract: A neural network device according to an embodiment includes an arithmetic circuit, a learning control circuit, and a bias reset circuit. The arithmetic circuit executes arithmetic processing according to a neural network using a plurality of weights each represented by a value of a first resolution and a plurality of biases each represented by a value in ternary. At the time of learning of the neural network, the learning control circuit repeats a learning process of updating each of the plurality of weights and each of the plurality of biases a plurality of times based on a result of the arithmetic processing according to the neural network performed by the arithmetic circuit. In each learning process, the bias reset circuit resets a bias randomly selected with a preset first probability among the plurality of biases to a median in the ternary.

Abstract: According to one embodiment, there is provided a neural network device including a neuron, a conversion part, a transmission part, a control part and a holding part. The conversion part converts a spike signal to a synapse current according to weight. The transmission part transmits the converted synapse current to the neuron. The control part determines transition of a state of the weight. The holding part holds the weight as a discrete state according to the determined transition of the state. The holding part includes an action part that stochastically operates based on a signal input from the control part to cause transition of the state of the weight. A cumulative probability of actions of the action part changes in a sigmoidal shape with respect to number of signal input times.

Abstract: A storage device according to an embodiment is for storing weights being continuous values. The storage device includes: a shift register, an initialization circuit, an update control circuit, and a readout control circuit. The shift resistor includes a plurality of cells, each being arranged in series and storing information. A position of each of the plurality of cells corresponds to the weight. The initialization circuit writes the information to a cell in the shift register. The update control circuit shifts a position of the cell storing the information in a direction corresponding to a sign of an update amount by a number of cells corresponding to an absolute value of the update amount. The readout control circuit reads out the information and outputs an output value according to the weight corresponding to the position of the cell storing the information.

Abstract: An arithmetic device includes N product-sum-operation circuits, a control circuit, and an output circuit. Each product-sum-operation circuit outputs intermediate signals obtained by binarizing a product-sum-operation value obtained by product-sum-operation of M input values of M input signals and M weight values. The control circuit inverts positive/negative of each M weight value at determining-timing when a given time elapses from input timing. Based on a delay time from the determination-timing to logic finalization of the intermediate signal for each N product-sum-operation circuit, the output circuit outputs an output signal representing a winner-product-sum-operation circuit for which the product-sum-operation value having a sign and the largest absolute value is calculated.

Abstract: A storage device according to an embodiment is for storing weights being continuous values. The storage device includes: a shift register, an initialization circuit, an update control circuit, and a readout control circuit. The shift resistor includes a plurality of cells, each being arranged in series and storing information. A position of each of the plurality of cells corresponds to the weight. The initialization circuit writes the information to a cell in the shift register. The update control circuit shifts a position of the cell storing the information in a direction corresponding to a sign of an update amount by a number of cells corresponding to an absolute value of the update amount. The readout control circuit reads out the information and outputs an output value according to the weight corresponding to the position of the cell storing the information.

Abstract: According to one embodiment, a computing device includes a first magnetic section, a first reading section, a memory section, and a computing section. The first reading section is configured to output a first signal corresponding to a magnetization state of a partial region of the first magnetic section. The computing section is configured to perform computation using the first signal when first information stored in the memory section is in a first state, and to perform computation using a reverse signal of the first signal when the first information is in a second state.