Patents by Inventor Koichi Mizushima
Koichi Mizushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11163534Abstract: According to one embodiment, an arithmetic device includes one or a plurality of arithmetic units. One of the one or plurality of arithmetic units includes a memory part including a plurality of memory regions, and an arithmetic part. At least one of the memory regions includes a memory element. The memory element is of a shift register-type.Type: GrantFiled: March 12, 2019Date of Patent: November 2, 2021Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Rie Sato, Koichi Mizushima
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Publication number: 20210279559Abstract: A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a determinator, a synaptic depressor, and a synaptic potentiator. The synaptic element has a variable weight and outputs, in response to input of a first spike signal, a synaptic signal having intensity adjusted in accordance with the weight. The neuron circuit outputs a second spike signal in a case where the synaptic signal is inputted and a predetermined firing condition for the synaptic signal is satisfied. The determinator determines whether or not the weight is to be updated on a basis of an output frequency of the second spike signal by the neuron circuit. The synaptic depressor performs depression operation for depressing the weight in a case where it is determined that the weight is to be updated. The synaptic potentiator performs potentiating operation for potentiating the weight.Type: ApplicationFiled: August 31, 2020Publication date: September 9, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshifumi NISHI, Kumiko NOMURA, Takao MARUKAME, Koichi MIZUSHIMA
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Publication number: 20210279558Abstract: A synaptic circuit according to an embodiment includes: a weight current circuit that applies a weight current corresponding to a weight value; an input switch that switches whether or not to cause the weight current circuit to apply the weight current; a capacitor that includes a first terminal and a second terminal, the first terminal being given a constant voltage; an output circuit that outputs the output signal corresponding to a capacitor voltage; a charge adjustment circuit that decreases or increases charges accumulated in the capacitor by drawing, from the second terminal, a capacitor current corresponding to a current value of the weight current, or supplying the capacitor current to the second terminal; and a control circuit that switches whether or not to reduce a current having a predetermined current value from the capacitor current in accordance with the weight value.Type: ApplicationFiled: August 28, 2020Publication date: September 9, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kumiko NOMURA, Takao MARUKAME, Yoshifumi NISHI, Koichi MIZUSHIMA
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Publication number: 20210216282Abstract: According to an embodiment, an arithmetic device includes a comparator, M cross switches, and M coefficient circuits. The comparator compares a first voltage generated at a first comparison terminal and a second voltage generated at a second comparison terminal. The M cross switches are provided corresponding to the M input signals. The M coefficient circuits are provided corresponding to the M coefficients, and each includes a first constant current source and a second constant current source. Each of the M cross switches performs switching between a straight state and a reverse state. In each of the M coefficient circuits, the first constant current source is connected between a positive output terminal of the corresponding coefficient circuit and a reference potential, and the second constant current source is connected between a negative output terminal of the corresponding coefficient circuit and the reference potential.Type: ApplicationFiled: August 27, 2020Publication date: July 15, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takao MARUKAME, Koichi MIZUSHIMA, Kumiko NOMURA, Yoshifumi NISHI
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Publication number: 20210081771Abstract: According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.Type: ApplicationFiled: February 26, 2020Publication date: March 18, 2021Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takao MARUKAME, Kumiko NOMURA, Yoshifumi NISHI, Koichi MIZUSHIMA
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Publication number: 20200394020Abstract: According to one embodiment, an arithmetic device includes an arithmetic circuit. The arithmetic circuit includes a memory part including a plurality of memory regions, and an arithmetic part. One of the memory regions includes a capacitance including a first terminal, and a first electrical circuit electrically connected to the first terminal and configured to output a voltage signal corresponding to a potential of the first terminal.Type: ApplicationFiled: March 10, 2020Publication date: December 17, 2020Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Rie SATO, Koichi MIZUSHIMA
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Patent number: 10698860Abstract: According to one embodiment, an arithmetic device includes one or a plurality of arithmetic units. One of the one or the arithmetic units includes a memory part including a plurality of memory regions, and an arithmetic part. At least one of the memory regions includes a line-shaped magnetic part.Type: GrantFiled: September 4, 2018Date of Patent: June 30, 2020Assignee: Kabushiki Kaisha ToshibaInventors: Rie Sato, Hayato Goto, Koichi Mizushima
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Publication number: 20200019377Abstract: According to one embodiment, an arithmetic device includes one or a plurality of arithmetic units. One of the one or plurality of arithmetic units includes a memory part including a plurality of memory regions, and an arithmetic part. At least one of the memory regions includes a memory element. The memory element is of a shift register-type.Type: ApplicationFiled: March 12, 2019Publication date: January 16, 2020Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Rie SATO, Koichi Mizushima
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Patent number: 10522172Abstract: According to one embodiment, an oscillator includes a first element. The first element includes first and second magnetic layers, and a first nonmagnetic layer. The first magnetic layer includes first and second magnetic films, and a first nonmagnetic film. The second magnetic film is provided between the second magnetic layer and the first magnetic film. The first nonmagnetic layer is provided between the second magnetic film and the second magnetic layer. An orientation of a first magnetization of the first magnetic film has a reverse component of an orientation of a second magnetization of the second magnetic film. A first magnetic field is applied to the first element. The first element is in a first state when a first current flows in the first element. An electrical resistance of the first element in the first state includes first and second electrical resistances repeating alternately.Type: GrantFiled: March 15, 2018Date of Patent: December 31, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Tazumi Nagasawa, Hirofumi Suto, Michinaga Yamagishi, Taro Kanao, Koichi Mizushima
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Patent number: 10424325Abstract: According to one embodiment, a magnetic head includes a first magnetic layer, a second magnetic layer, an intermediate layer, a magnetic pole, a first terminal, and a second terminal. The second magnetic layer is separated from the first magnetic layer in a first direction. The intermediate layer is provided between the first magnetic layer and the second magnetic layer. A second direction from the first magnetic layer toward the magnetic pole crosses the first direction. The first terminal is electrically connected to the intermediate layer. The second terminal is electrically connected to the second magnetic layer.Type: GrantFiled: August 31, 2017Date of Patent: September 24, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Hirofumi Suto, Kiwamu Kudo, Tazumi Nagasawa, Taro Kanao, Rie Sato, Koichi Mizushima
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Publication number: 20190278740Abstract: According to one embodiment, an arithmetic device includes one or a plurality of arithmetic units. One of the one or the arithmetic units includes a memory part including a plurality of memory regions, and an arithmetic part. At least one of the memory regions includes a line-shaped magnetic part.Type: ApplicationFiled: September 4, 2018Publication date: September 12, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Rie SATO, Hayato GOTO, Koichi MIZUSHIMA
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Patent number: 10210894Abstract: According to one embodiment, a magnetic recording medium includes a first layer and a second layer. The first layer includes a first magnetic region, a second magnetic region, and a nonmagnetic region provided between the first and second magnetic regions. A direction from the second magnetic region toward the first magnetic region is along a first direction. The second layer includes third, fourth, and fifth magnetic regions. At least a portion of the fifth magnetic region is provided between the third and fourth magnetic regions. The third magnetic region overlaps the first magnetic region in a second direction crossing the first direction. The fourth magnetic region overlaps the second magnetic region in the second direction. The fifth magnetic region overlaps the nonmagnetic region in the second direction. An easy magnetization axis of each of the first to fifth magnetic regions is aligned with the second direction.Type: GrantFiled: February 15, 2018Date of Patent: February 19, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Hirofumi Suto, Taro Kanao, Tazumi Nagasawa, Rie Sato, Koichi Mizushima
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Publication number: 20180374502Abstract: According to one embodiment, an oscillator includes a first element. The first element includes first and second magnetic layers, and a first nonmagnetic layer. The first magnetic layer includes first and second magnetic films, and a first nonmagnetic film. The second magnetic film is provided between the second magnetic layer and the first magnetic film. The first nonmagnetic layer is provided between the second magnetic film and the second magnetic layer. An orientation of a first magnetization of the first magnetic film has a reverse component of an orientation of a second magnetization of the second magnetic film. A first magnetic field is applied to the first element. The first element is in a first state when a first current flows in the first element An electrical resistance of the first element in the first state includes first and second electrical resistances repeating alternately.Type: ApplicationFiled: March 15, 2018Publication date: December 27, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tazumi NAGASAWA, Hirofumi SUTO, Michinaga YAMAGISHI, Taro KANAO, Koichi MIZUSHIMA
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Publication number: 20180335973Abstract: According to one embodiment, a computing device includes a first magnetic section, a first reading section, a memory section, and a computing section. The first reading section is configured to output a first signal corresponding to a magnetization state of a partial region of the first magnetic section. The computing section is configured to perform computation using the first signal when first information stored in the memory section is in a first state, and to perform computation using a reverse signal of the first signal when the first information is in a second state.Type: ApplicationFiled: March 19, 2018Publication date: November 22, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Rie SATO, Koichi Mizushima, Hayato Goto
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Patent number: 10127931Abstract: According to one embodiment, a magnetic recording and reproducing device includes a magnetic recording medium, a magnetic head, and a controller. The controller implements a first operation and a second operation. The first operation is implemented in a first information recording interval including a first recording interval and a first non-recording interval. The second operation is implemented in a second information recording interval including a second recording interval and a second non-recording interval. The first operation includes in the first recording interval, generating a first signal magnetic field from the magnetic head, and in the first non-recording interval, generating a first non-signal magnetic field from the magnetic head. The second operation includes in the second recording interval, generating a second signal magnetic field from the magnetic head, and in the second non-recording interval, generating a second non-signal magnetic field from the magnetic head.Type: GrantFiled: September 15, 2016Date of Patent: November 13, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Hirofumi Suto, Kiwamu Kudo, Tazumi Nagasawa, Taro Kanao, Rie Sato, Koichi Mizushima
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Publication number: 20180267087Abstract: According to one embodiment, a microwave sensor includes a first stacked body and a first controller. The first stacked body includes a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The first controller is electrically connected to the first magnetic layer and the second magnetic layer. The first controller is configured to supply a current to the first stacked body and is configured to sense a value corresponding to a first electrical resistance between the first magnetic layer and the second magnetic layer. A second magnetization of the second magnetic layer is aligned with a first direction from the first magnetic layer toward the second magnetic layer. The value corresponding to the first electrical resistance changes according to a microwave.Type: ApplicationFiled: September 15, 2017Publication date: September 20, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tazumi NAGASAWA, Hirofumi SUTO, Michinaga YAMAGISHI, Taro KANAO, Kiwamu KUDO, Koichi MIZUSHIMA
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Publication number: 20180204589Abstract: According to one embodiment, a magnetic head includes a first magnetic layer, a second magnetic layer, an intermediate layer, a magnetic pole, a first terminal, and a second terminal. The second magnetic layer is separated from the first magnetic layer in a first direction. The intermediate layer is provided between the first magnetic layer and the second magnetic layer. A second direction from the first magnetic layer toward the magnetic pole crosses the first direction. The first terminal is electrically connected to the intermediate layer. The second terminal is electrically connected to the second magnetic layer.Type: ApplicationFiled: August 31, 2017Publication date: July 19, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hirofumi SUTO, Kiwamu KUDO, Tazumi NAGASAWA, Taro KANAO, Rie SATO, Koichi MIZUSHIMA
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Patent number: 10027334Abstract: According to an embodiment, a computing apparatus includes spin torque oscillators, an interaction unit, a variable direct-current supply device, and a measuring unit. The interaction unit controls an interaction between the spin torque oscillators. The variable direct-current supply device supplies a current to induce oscillations of the spin torque oscillators. The measuring unit measures AC signals obtained from the spin torque oscillators.Type: GrantFiled: September 9, 2016Date of Patent: July 17, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Taro Kanao, Tazumi Nagasawa, Hayato Goto, Kiwamu Kudo, Hirofumi Suto, Michinaga Yamagishi, Koichi Mizushima, Rie Sato
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Patent number: 9984723Abstract: A magnetic recording and reproducing apparatus for recording and reproducing bit information comprising a magnetic head having a spin torque oscillator configured to readout bit information which is recorded on a magnetic recording medium, a detector configured to detect amplitude of a first signal, the first signal which is to reproduce the bit information, and a controller configured to control the magnetic head so as to read the bit information recorded on the magnetic recording medium when the amplitude of the first signal detected by the detector is smaller than a predetermined value.Type: GrantFiled: February 28, 2017Date of Patent: May 29, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tazumi Nagasawa, Taro Kanao, Michinaga Yamagishi, Hirofumi Suto, Kiwamu Kudo, Rie Sato, Koichi Mizushima
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Patent number: 9911438Abstract: According to one embodiment, a magnetic recording and reproducing device includes a magnetic recording medium, and a magnetic head including a first reproducing unit. The first reproducing unit includes a first magnetic field generator separated from the magnetic recording medium in a first direction, and a first stacked body. At least a portion of the first stacked body is provided between the magnetic recording medium and the first magnetic field generator in the first direction. The first stacked body includes a first magnetic layer, a second magnetic layer separated from the first magnetic layer in a second direction crossing the first direction, and a first intermediate layer provided between the first magnetic layer and the second magnetic layer. The first stacked body performs an operation of generating a first alternating magnetic field. The first magnetic field generator generates a first magnetic field.Type: GrantFiled: February 21, 2017Date of Patent: March 6, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Taro Kanao, Hirofumi Suto, Koichi Mizushima, Rie Sato