Abstract: A multi-port semiconductor memory in which wrong read-out due to coupling noise is hardly generated and operation speed is fast is provided. When data are written in memory cells from a pair of bit lines for one port, NMOS transistors become on. Electrical potential only at a low-level side is pulled up between the pair of bit lines, because electrical potential at a high-level side is approximately equivalent to power potential. Accordingly, when one of adjacent bit lines is on high-level and the other is on low-level, potential difference is reduced by the pull-up, resulting in reduction of generating time of the coupling noise. Although read-out of data can not be performed while the coupling noise is being generated, since the concerned generating time is reduced in the invention, the operation speed is substantially fast.

Abstract: A multi-port semiconductor memory in which wrong read-out due to coupling noise is hardly generated and operation speed is fast is provided. When data are written in memory cells from a pair of bit lines for one port, NMOS transistors become on. Electrical potential only at a low-level side is pulled up between the pair of bit lines, because electrical potential at a high-level side is approximately equivalent to power potential. Accordingly, when one of adjacent bit lines is on high-level and the other is on low-level, potential difference is reduced by the pull-up, resulting in reduction of generating time of the coupling noise. Although read-out of data can not be performed while the coupling noise is being generated, since the concerned generating time is reduced in the invention, the operation speed is substantially fast.

Abstract: A semiconductor integrated circuit operating in an active state and a sleep state has a power line that is branched through a first transistor to a first virtual power line and through a second transistor to a second virtual power line. The first transistor is switched on in the active state and off in the sleep state; the second transistor is switched off in the active state and on in the sleep state. The first virtual power line powers logic circuits. The second power line powers a memory circuit that stores necessary logic-circuit signal levels during the sleep state. The memory circuit does not consume power in the active state.

Abstract: A semiconductor storage device in the invention comprises a first control transistor which is connected between a bit line and a first node and whose control terminal is connected to a word line, a data retention circuit which includes a first transistor that is connected between the first node and a second reference voltage terminal, as well as a first inverter that includes a second transistor connected between a second node and the second reference voltage terminal, and a substrate potential control circuit which selectively alters a substrate potential of the first transistor so as to make a threshold voltage of the first transistor higher as compared with threshold voltages of the first control transistor and the second transistor. Thus, it is permitted to provide the semiconductor storage device of static type which realizes a reduced layout area and a lower-dissipation-power operation while ensuring the reliability and high operating speed of the write and read of data.

Abstract: As a storage cell for surface mounting which reduces the mounting area, increases the reliability of soldering and realizes high-density mounting, provided is a storage cell for surface mounting having: a polar storage cell housing a component between a case and a top cover and sealed with an insulator; an anode terminal connected to an outer surface of the case; and a cathode terminal connected to an outer surface of the top cover. In this storage cell, the anode terminal is provided with an external connection connected to a printed wiring board, the cathode electrode is provided with a mounting-fixing portion connected to an external connection connected to the printed wiring board and the top cover, and a plated layer is formed on the external connections of the anode terminal and cathode terminal and on the mounting-fixing portion of the cathode terminal.

Abstract: A semiconductor integrated circuit operating in an active state and a sleep state has a power line that is branched through a first transistor to a first virtual power line and through a second transistor to a second virtual power line. The first transistor is switched on in the active state and off in the sleep state; the second transistor is switched off in the active state and on in the sleep state. The first virtual power line powers logic circuits. The second power line powers a memory circuit that stores necessary logic-circuit signal levels during the sleep state. The memory circuit does not consume power in the active state.

Abstract: A content addressable memory includes a seek access circuit with four transistors connected in series between a pair of bit lines. The two inner transistors are driven by a data storage circuit; the outer two transistors function as enable transistors. A level shifting circuit receives an enable signal and shifts one or both of the logic levels of the enable signal so as to widen the potential difference between them. The shifted enable signal drives the enable transistors in the seek access circuit. Shifting the high logic level of the enable signal upward speeds up seek access by reducing the on-resistance of the enable transistors. Shifting the low logic level of the enable signal downward reduces subthreshold leakage through the seek access circuit, thereby reducing current consumption, speeding up read and write access, and preventing access errors.

Abstract: As a storage cell for surface mounting which reduces the mounting area, increases the reliability of soldering and realizes high-density mounting, provided is a storage cell for surface mounting having: a polar storage cell housing a component between a case and a top cover and sealed with an insulator; an anode terminal connected to an outer surface of the case; and a cathode terminal connected to an outer surface of the top cover. In this storage cell, the anode terminal is provided with an external connection connected to a printed wiring board, the cathode electrode is provided with a mounting-fixing portion connected to an external connection connected to the printed wiring board and the top cover, and a plated layer is formed on the external connections of the anode terminal and cathode terminal and on the mounting-fixing portion of the cathode terminal.

Abstract: A semiconductor storage device in the invention comprises a first control transistor which is connected between a bit line and a first node and whose control terminal is connected to a word line, a data retention circuit which includes a first transistor that is connected between the first node and a second reference voltage terminal, as well as a first inverter that includes a second transistor connected between a second node and the second reference voltage terminal, and a substrate potential control circuit which selectively alters a substrate potential of the first transistor so as to make a threshold voltage of the first transistor higher as compared with threshold voltages of the first control transistor and the second transistor. Thus, it is permitted to provide the semiconductor storage device of static type which realizes a reduced layout area and a lower-dissipation-power operation while ensuring the reliability and high operating speed of the write and read of data.

Abstract: A writing operation control circuit for a semiconductor memory includes a driving circuit which operates to perform a writing operation in response to a writing data signal, the driving circuit having a specific threshold voltage; a first voltage control circuit which selectively outputs first and second supply voltages to the driving circuit in response to a logical level of a write controlling signal; and a second voltage control circuit which selectively outputs third and fourth supply voltages to the driving circuit in response to a logical level of the write controlling signal. The second supply voltage is higher than the first supply voltage, the first supply voltage is higher than the fourth supply voltage, and the fourth supply voltage is higher than the third supply voltage.

Abstract: A semiconductor driver circuit includes a first inverter circuit that inverts an input voltage and supplies a first inverted voltage, and a second inverter circuit that inverts the first inverted voltage and outputs a second inverted voltage. The second inverter circuit includes a first conduction type transistor, such as a PMOS transistor, and a second conduction type transistor, different from the first conduction type transistor, such as an NMOS transistor. The driver circuit further includes a substrate voltage supply circuit that supplies voltages to the substrate of the first conduction type transistor and the substrate of the second conduction type transistor, respectively, according to the second inverted voltage, and a substrate voltage control circuit that adjusts the substrate voltages applied to either or both of the first and second conduction type transistors, according to the second inverted voltage, in order to lessen the power consumption of the driver circuit.

Abstract: The present invention comprises first unit cells each including PMOS transistors and NMOS transistors, each transistor having a first threshold voltage, second unit cells each including PMOS transistors and NMOS transistors, each transistor having a second threshold voltage, a unit cell array comprised of the first and second unit cells laid in array form, a power switch disposed around the unit cell array and comprised of the PMOS transistors and NMOS transistors each having the second threshold voltage, and input/output circuits disposed around the unit cell array.

Abstract: The invention intends to provide a semiconductor integrated circuit including MOS transistors, which is able to operate at a high-speed with a low power supply voltage in the active mode, and to reduce the power consumption resulting from the leakage current in the standby mode.In view of the foregoing object, the semiconductor integrated circuit of the invention is comprised of a first power supply line to which a first power supply potential is supplied, a virtual power supply line, a logic circuit connected to the virtual power supply line, a power control transistor provided between the first power supply line and the virtual power supply line, having a control electrode to which a first control signal is inputted, a second power supply line to which a second power supply potential is supplied, and a substrate potential control circuit connected to a substrate on which the power control transistor is formed, the first power supply line, and the second power supply line.