Patents by Inventor Koichi Nagai

Koichi Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240303189
    Abstract: According to one embodiment, a controller, in response to receiving, from a host, a first command requesting secure erase of secure erase target data associated with a first logical area identifier, stores a copy of first mapping information that corresponds to the first logical area identifier, among mapping information that is included in a first table. The controller executes at least a data erase operation for one or more first blocks storing the secure erase target data. In a first mode, the controller, in response to receiving, from the host, a read command that specifies the first logical area identifier, reads data from a storage location corresponding to a first physical address that is mapped to the first logical area identifier in the copy of the first mapping information.
    Type: Application
    Filed: March 7, 2024
    Publication date: September 12, 2024
    Applicant: Kioxia Corporation
    Inventor: Koichi NAGAI
  • Patent number: 12056399
    Abstract: According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: August 6, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Shinichi Kanno, Koichi Nagai
  • Publication number: 20240248797
    Abstract: According to one embodiment, an information processing system includes a host and memory systems. A first memory system stores first data in a nonvolatile memory. A second memory system stores second data in a nonvolatile memory. The host transmits first update data to the first memory system and transmits second update data to the second memory system. The first memory system generates first XOR data by performing an XOR operation on at least the first data and the first update data, and transmits the first XOR data to the second memory system. The second memory system generates second XOR data by performing an XOR operation on the second data, the second update data, and the first XOR data, and transmits the second XOR data to a third memory system.
    Type: Application
    Filed: June 9, 2023
    Publication date: July 25, 2024
    Inventors: Hiroyasu NAKATSUKA, Koichi NAGAI
  • Patent number: 11913842
    Abstract: As a temperature measurement apparatus using a surface acoustic wave of a piezoelectric substrate that performs temperature measurement wirelessly and without power supply, the temperature measurement apparatus accurately measures the temperature of the thermocouple tip end by analyzing the frequency characteristics of the surface acoustic wave propagating on the piezoelectric substrate and including temperature information of the piezoelectric substrate, and detecting change in propagation time of the surface acoustic wave of the piezoelectric substrate that is changed by the electromotive force of the thermocouple.
    Type: Grant
    Filed: May 22, 2022
    Date of Patent: February 27, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Koichi Nagai, Naofumi Hino
  • Patent number: 11899962
    Abstract: According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores first data in the nonvolatile memory, performs a first transmission of a write request associated with the first data to the memory system, and stores management data including information equivalent to the write request in the nonvolatile memory. In response to receiving a first response to the write request transmitted in the first transmission, the CPU adds, to the management data, information indicating that the first response has been received. The CPU deletes the first data and the management data in response to receiving a second response to the write request transmitted in the first transmission after receiving the first response.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: February 13, 2024
    Assignee: Kioxia Corporation
    Inventors: Naoki Esaka, Koichi Nagai, Toyohide Isshi
  • Publication number: 20230305754
    Abstract: According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.
    Type: Application
    Filed: May 31, 2023
    Publication date: September 28, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Shinichi KANNO, Koichi NAGAI
  • Publication number: 20230297246
    Abstract: According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores, to the nonvolatile memory, first data, and management data including information equivalent to a write command associated with the first data and designating a first LBA range, and performs a first transmission of the write command to a memory system. When writing of second data to a second LBA range including a third LBA range that is at least a portion of the first LBA range or deallocation of the second LBA range is requested before a second response to the write command is received, the CPU transmits, to the system, a command to cancel writing to at least the third LBA range from writing of the first data to the first LBA range in accordance with the write command.
    Type: Application
    Filed: September 7, 2022
    Publication date: September 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Koichi NAGAI, Naoki ESAKA, Toyohide ISSHI
  • Patent number: 11704069
    Abstract: According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: July 18, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Koichi Nagai
  • Publication number: 20230153012
    Abstract: According to one embodiment, a memory system includes a non-volatile memory with a plurality of blocks. The minimum unit of a data erasing operation in the memory system is a block. A controller is electrically connected to the non-volatile memory and configured to execute, in response to a first command from a host requesting a secure erase of secure erase target data stored in a first logical area identified by a first logical area identifier, a copy operation copying valid data other than any secure erase target data from one or more first blocks of the plurality in which the secure erase target data is stored to one or more copy destination blocks of the plurality. The controller executes the data erasing operation on the one or more first blocks after the copy operation.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Inventor: Koichi NAGAI
  • Publication number: 20230070397
    Abstract: According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores first data in the nonvolatile memory, performs a first transmission of a write request associated with the first data to the memory system, and stores management data including information equivalent to the write request in the nonvolatile memory. In response to receiving a first response to the write request transmitted in the first transmission, the CPU adds, to the management data, information indicating that the first response has been received. The CPU deletes the first data and the management data in response to receiving a second response to the write request transmitted in the first transmission after receiving the first response.
    Type: Application
    Filed: March 3, 2022
    Publication date: March 9, 2023
    Applicant: Kioxia Corporation
    Inventors: Naoki ESAKA, Koichi NAGAI, Toyohide ISSHI
  • Patent number: 11586377
    Abstract: According to one embodiment, a memory system includes a non-volatile memory with a plurality of blocks. The minimum unit of a data erasing operation in the memory system is a block. A controller is electrically connected to the non-volatile memory and configured to execute, in response to a first command from a host requesting a secure erase of secure erase target data stored in a first logical area identified by a first logical area identifier, a copy operation copying valid data other than any secure erase target data from one or more first blocks of the plurality in which the secure erase target data is stored to one or more copy destination blocks of the plurality. The controller executes the data erasing operation on the one or more first blocks after the copy operation.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: February 21, 2023
    Assignee: Kioxia Corporation
    Inventor: Koichi Nagai
  • Publication number: 20220390293
    Abstract: As a temperature measurement apparatus using a surface acoustic wave of a piezoelectric substrate that performs temperature measurement wirelessly and without power supply, the temperature measurement apparatus accurately measures the temperature of the thermocouple tip end by analyzing the frequency characteristics of the surface acoustic wave propagating on the piezoelectric substrate and including temperature information of the piezoelectric substrate, and detecting change in propagation time of the surface acoustic wave of the piezoelectric substrate that is changed by the electromotive force of the thermocouple.
    Type: Application
    Filed: May 22, 2022
    Publication date: December 8, 2022
    Inventors: KOICHI NAGAI, NAOFUMI HINO
  • Patent number: 11511364
    Abstract: A method and an apparatus for collecting flux are disclosed. A rosin particle contained in an atmosphere gas, and a vapor of a solvent or an atomized solvent particle are mixed in a mixing section upstream of a flux collection unit-side inlet, and a gas containing a mixed particle is cleaned by electrostatic precipitation. The solvent particle adheres to the rosin particle, and forms an aggregate of larger particle size.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: November 29, 2022
    Assignee: PANASONIC INTELLETUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naoshi Yamaguchi, Koichi Nagai, Yasuyuki Takano, Toshiro Kanda
  • Publication number: 20220147283
    Abstract: According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 12, 2022
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Koichi NAGAI
  • Patent number: 11269558
    Abstract: According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: March 8, 2022
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Koichi Nagai
  • Patent number: 11262129
    Abstract: A gas phase type heating method includes loading an object into a vapor heating furnace or a heating furnace via a loading/unloading portion, cooling vapor of a heat transfer liquid by a cooler provided above the loading/unloading portion in the vapor heating furnace, and causing a gas to go in and out, making a pressure in a continuous furnace uniform, and heating the loaded object, by a connection portion that is provided above the cooler and has a pressure loss smaller than a pressure loss of the loading/unloading portion.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: March 1, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Koichi Nagai
  • Patent number: 11232044
    Abstract: According to one embodiment, a data storage apparatus includes a controller with a data protection function. The controller manages first and second personal identification data. The first personal identification data only includes authority to request inactivation of the data protection function. The second personal identification data includes authority to request inactivation of the data protection function and activation of the data protection function. The controller permits setting of the first personal identification data, when the second personal identification data is used for successful authentication and the first personal identification data is an initial value, or when the data protection function is in an inactive state.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: January 25, 2022
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Isozaki, Koichi Nagai
  • Publication number: 20220006639
    Abstract: A non-transitory recording medium storing an information processing program executable by a computer to perform a process, the process comprising: executing an authenticity check of written document data in a case in which a request for an authenticity check of the written document data has been received from a requesting party; transmitting an inquiry result from the authenticity check to the requesting party; storing information regarding the requesting party and identification information for the written document data in association with each other in a first storage section, in response to either the authenticity check request from the requesting party or transmission of the authenticity check inquiry result to the requesting party; and notifying an issuing party of the written document data, as pre-stored in a second storage section, of information regarding the requesting party associated with the written document data identification information.
    Type: Application
    Filed: September 21, 2021
    Publication date: January 6, 2022
    Applicant: FUJITSU LIMITED
    Inventors: Koichi Nagai, Masahiro Shimada
  • Publication number: 20210405907
    Abstract: According to one embodiment, a memory system includes a non-volatile memory with a plurality of blocks. The minimum unit of a data erasing operation in the memory system is a block. A controller is electrically connected to the non-volatile memory and configured to execute, in response to a first command from a host requesting a secure erase of secure erase target data stored in a first logical area identified by a first logical area identifier, a copy operation copying valid data other than any secure erase target data from one or more first blocks of the plurality in which the secure erase target data is stored to one or more copy destination blocks of the plurality. The controller executes the data erasing operation on the one or more first blocks after the copy operation.
    Type: Application
    Filed: February 25, 2021
    Publication date: December 30, 2021
    Inventor: Koichi NAGAI
  • Patent number: 11148217
    Abstract: A reflow furnace that can reduce both the flux clinging defect in a circuit board, and the thermal cracking defect in an electronic component has a heat zone in which a circuit board with a mounted electronic component is heated, and a cooling zone in which the heated circuit board is cooled, and includes: a shield disposed between the heat zone and the cooling zone and having an opening for passage of the circuit board; and a tunnel-like cover physically coupled to the opening and extending along a transport direction of the circuit board.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 19, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Naoshi Yamaguchi, Toshiro Kanda, Yasuyuki Takano, Koichi Nagai