Patents by Inventor Koichi Nagai

Koichi Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160310891
    Abstract: To provide a solvent separator for purifying an exhaust atmosphere efficiently in solvent removal from the exhaust atmosphere containing a vaporized solvent by the heating exhausted from an exhaust generator, so that the vaporized solvent does not slip through an electrode for collecting the solvent and is positively led to the electrode. An electrode is arranged in a first wall surface of a casing of a solvent separation unit having a circular cylindrical shape, thereby inducing a vaporized solvent in an exhaust atmosphere to the electrode by a fan and discharging the solvent to the outside of the separator with part of the peripheral exhaust atmosphere while attracting the solvent to the electrode by an electric field of the electrode.
    Type: Application
    Filed: January 17, 2016
    Publication date: October 27, 2016
    Inventors: TOMOHIRO UJINO, TERUTSUGU SEGAWA, KOICHI NAGAI
  • Patent number: 9396137
    Abstract: According to one embodiment, a storage device includes, when power is supplied to a storage unit, counting of an elapsed time is started. If a command is input from a host device, and the elapsed time from input of a previous command to input of a current command is calculated based on time information clocked by the host device and on a counter value counted until the corresponding command is input. Matching of the time information is determined based on a temporal relation between the adding result of adding the calculated elapsed time to the time information included in the previous command and the time information included in the current command. When the mismatching is determined, data in the storage unit is invalidated.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: July 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nagai, Mitsunori Tadokoro, Teruji Yamakawa, Kazuo Nakashima
  • Publication number: 20160172016
    Abstract: According to one embodiment, a semiconductor device includes, for example, a circuit board, a plurality of elements, a plurality of controllers, and a first signal line. The elements are provided on the circuit board. The elements each include a memory. The controllers each are configured to control read of data from the memory. The controllers each are configured to control write of data into the memory. A control signal is transmitted through the first signal line. The first signal line is used in common by the controllers.
    Type: Application
    Filed: March 10, 2015
    Publication date: June 16, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Manabu MATSUMOTO, Katsuya MURAKAMI, Koichi NAGAI
  • Publication number: 20160154745
    Abstract: According to one embodiment, a memory device includes: a nonvolatile semiconductor memory; and a controller which controls the semiconductor memory. The controller includes: a first memory which stores a first key; a second memory which stores a second key; a first generator which generates a third key based on a random number; a second generator which generates a fourth key based on the first key and the third key; and an encryptor which encrypts the second key with the third key. The third key and the encrypted second key are stored in a host device enabled to access the memory device.
    Type: Application
    Filed: December 2, 2015
    Publication date: June 2, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi NAGAI, Yuji Kashiwagi
  • Patent number: 9354818
    Abstract: According to one embodiment, a data storing method includes saving data stored in a memory device to a host device and verifying validity or accuracy of the data saved in the host device.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: May 31, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yaotung Kuo, Koichi Nagai, Shoji Sawamura, Nobuhiro Kondo
  • Publication number: 20160125950
    Abstract: According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the controller and driven by a second power supply voltage, and a switch element determining whether the second power supply voltage is applied to the nonvolatile memory. The controller is configured to turn off the switch element in a first mode and turn on the switch element in a second mode.
    Type: Application
    Filed: March 9, 2015
    Publication date: May 5, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi NAGAI, Katsuya Murakami, Shinji Honjo, Satoru Fukuchi, Akira Tanimoto, Isao Ozawa
  • Patent number: 9304685
    Abstract: According to the embodiments, a storage array system includes a plurality of storage units, and a host device. The host device determines whether first data, which is restored from data in the storage units other than a replaced first storage unit, is identical with data indicated by a first function. The host device transmits and writes the first data to the first storage unit, when the first data is not identical with the data indicated by the first function. The host device transmits a deletion notification to the first storage unit, when the first data is identical with the data indicated by the first function.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Hashimoto, Koichi Nagai
  • Patent number: 9275947
    Abstract: A semiconductor device includes a substrate, a sealing portion, a controller, a semiconductor chip, and a plurality of differential signal balls. The substrate has a first surface and a second surface positioned on a side opposite to the first surface. The sealing portion is formed on the first surface of the substrate. The controller is covered with the sealing portion. The semiconductor chip is electrically connected to the controller, and is covered with the sealing portion. The plurality of differential signal balls are formed on the second surface of the substrate. At least some of the plurality of differential signal balls are arranged substantially parallel to one side of the substrate.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: March 1, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Isao Ozawa, Isao Maeda, Yasuo Kudo, Koichi Nagai, Katsuya Murakami, Akira Tanimoto
  • Publication number: 20160041793
    Abstract: According to embodiments, a controller comprises a write control unit that performs writing in a nonvolatile semiconductor memory, and an area management unit that causes the write control unit to perform write processing until a spare area not storing valid data is not present in the nonvolatile semiconductor memory, and transmits an error to a host when the spare area is not present.
    Type: Application
    Filed: October 20, 2015
    Publication date: February 11, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Koichi NAGAI
  • Publication number: 20160018994
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller reads write data associated with a first write command from a host memory by a unit of a first size in response to the first write command from a host. The host memory is included in the host. In a case where the size of first data not yet read from the host memory out of the write data is less than a second size, in response to a second write command, the controller reads second data of the second size and writes the read second data into the nonvolatile memory. The second data includes the first data and third data included in write data associated with the second write command. After writing the second data into the nonvolatile memory, the controller transmits a notice for the first write command to the host.
    Type: Application
    Filed: March 3, 2015
    Publication date: January 21, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yukimasa MIYAMOTO, Koichi NAGAI
  • Publication number: 20160011818
    Abstract: According to an embodiment, when a storage status of a first storage unit is recognized as a protected state, a control unit writes data to a second storage unit. When a read target address is recorded in a data migration log area, the control unit reads data from the second storage unit. When the read target address is not recorded in the data migration log area, the control unit reads data from the first storage unit.
    Type: Application
    Filed: September 10, 2015
    Publication date: January 14, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke HASHIMOTO, Koichi Nagai, Takanori Watanabe
  • Patent number: 9201784
    Abstract: According to embodiments, a controller comprises a write control unit that performs writing in a nonvolatile semiconductor memory, and an area management unit that causes the write control unit to perform write processing until a spare area not storing valid data is not present in the nonvolatile semiconductor memory, and transmits an error to a host when the spare area is not present.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 1, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Nagai
  • Publication number: 20150309946
    Abstract: According to one embodiment, a storage device includes, when power is supplied to a storage unit, counting of an elapsed time is started. If a command is input from a host device, and the elapsed time from input of a previous command to input of a current command is calculated based on time information clocked by the host device and on a counter value counted until the corresponding command is input. Matching of the time information is determined based on a temporal relation between the adding result of adding the calculated elapsed time to the time information included in the previous command and the time information included in the current command. When the mismatching is determined, data in the storage unit is invalidated.
    Type: Application
    Filed: June 11, 2015
    Publication date: October 29, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi NAGAI, Mitsunori Tadokoro, Teruji Yamakawa, Kazuo Nakashima
  • Publication number: 20150242141
    Abstract: According to one embodiment, a data storing method includes saving data stored in a memory device to a host device and verifying validity or accuracy of the data saved in the host device.
    Type: Application
    Filed: September 3, 2014
    Publication date: August 27, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yaotung KUO, Koichi Nagai, Shoji Sawamura, Nobuhiro Kondo
  • Publication number: 20150235020
    Abstract: According to one embodiment, a storage device that has a nonvolatile semiconductor memory includes an authentication information storage unit that previously stores first apparatus authentication information to authenticate an authorized host device and first user authentication information to authenticate an authorized user. The storage device executes apparatus authentication on the basis of second apparatus authentication information received from a newly connected host device and the first apparatus authentication information in the authentication information storage unit and executes an invalidation process of user data stored in the nonvolatile semiconductor memory, when the apparatus authentication is failed.
    Type: Application
    Filed: April 29, 2015
    Publication date: August 20, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi NAGAI, Mitsunori TADOKORO, Teruji YAMAKAWA, Kazuo NAKASHIMA
  • Publication number: 20150200008
    Abstract: According to one embodiment, a semiconductor package includes a package substrate, a controller chip, a semiconductor memory chip, a temperature sensor, a seal portion, and a plurality of solder balls. The controller chip and the semiconductor memory chip are provided on a first surface of the package substrate. The temperature sensor is provided at a position along an edge of the first surface, which is at a center portion separated away from corner portions. The plurality of solder balls is provided on a second surface that is at an opposite side of the first surface.
    Type: Application
    Filed: July 1, 2014
    Publication date: July 16, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Isao OZAWA, Akira TANIMOTO, Eigo MATSUURA, Katsuya MURAKAMI, Yasuo KUDO, Koichi NAGAI
  • Patent number: 9081943
    Abstract: According to one embodiment, a storage device includes, when power is supplied to a storage unit, counting of an elapsed time is started. If a command is input from a host device, and the elapsed time from input of a previous command to input of a current command is calculated based on time information clocked by the host device and on a counter value counted until the corresponding command is input. Matching of the time information is determined based on a temporal relation between the adding result of adding the calculated elapsed time to the time information included in the previous command and the time information included in the current command. When the mismatching is determined, data in the storage unit is invalidated.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Nagai, Mitsunori Tadokoro, Teruji Yamakawa, Kazuo Nakashima
  • Patent number: 9064108
    Abstract: According to one embodiment, a storage device that has a nonvolatile semiconductor memory includes an authentication information storage unit that previously stores first apparatus authentication information to authenticate an authorized host device and first user authentication information to authenticate an authorized user. The storage device executes apparatus authentication on the basis of second apparatus authentication information received from a newly connected host device and the first apparatus authentication information in the authentication information storage unit and executes an invalidation process of user data stored in the nonvolatile semiconductor memory, when the apparatus authentication is failed.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: June 23, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Nagai, Mitsunori Tadokoro, Teruji Yamakawa, Kazuo Nakashima
  • Publication number: 20150137363
    Abstract: A semiconductor device includes a substrate, a sealing portion, a controller, a semiconductor chip, and a plurality of differential signal balls. The substrate has a first surface and a second surface positioned on a side opposite to the first surface. The sealing portion is formed on the first surface of the substrate. The controller is covered with the sealing portion. The semiconductor chip is electrically connected to the controller, and is covered with the sealing portion. The plurality of differential signal balls are formed on the second surface of the substrate. At least some of the plurality of differential signal balls are arranged substantially parallel to one side of the substrate.
    Type: Application
    Filed: February 26, 2014
    Publication date: May 21, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Isao OZAWA, Isao MAEDA, Yasuo KUDO, Koichi NAGAI, Katsuya MURAKAMI, Akira TANIMOTO
  • Publication number: 20150130059
    Abstract: According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board.
    Type: Application
    Filed: February 19, 2014
    Publication date: May 14, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Isao OZAWA, Isao MAEDA, Yasuo KUDO, Koichi NAGAI, Katsuya MURAKAMI