Patents by Inventor Koichi Ohto

Koichi Ohto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7132732
    Abstract: A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure having a metal wiring pattern formed therein. The insulating layer structure includes a first SiOCH layer, a second SiOCH layer formed on the first SiOCH layer, and a silicon dioxide (SiO2) layer formed on the second SiOCH layer. The second SiOCH layer features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer, and an oxygen (O) density higher than that of the first SiOCH layer.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: November 7, 2006
    Assignee: NEC Electronics Corporation
    Inventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Sadayuki Ohnishi, Koji Arita, Ryohei Kitao, Yoichi Sasaki
  • Patent number: 7119441
    Abstract: In a semiconductor device, an interlevel insulating film formed between a Cu interconnection, formed by damascene, and an upper metal interconnection layer on it has a multilayered structure made up of a Cu diffusion preventive insulating layer and another insulating film. The Cu diffusion preventive insulating layer has a multilayered structure made up of not less than two layers. A method for manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: October 10, 2006
    Assignee: NEC Electronics Corporation
    Inventors: Koichi Ohto, Takayuki Matsui
  • Publication number: 20060208361
    Abstract: A semiconductor chip 100 includes a semiconductor substrate (not shown), and a stacked film 150 formed over the semiconductor substrate, which includes carbon-containing insulating films such as a first interlayer insulating film 106, and carbon-free insulating films such as an underlying layer 102 and a top cover film 124. The end faces of the carbon-free insulating films herein are located on the outer side of the end faces of the carbon-containing insulating films. The carbon composition of the carbon-containing insulating films is lowered in the end portions thereof than in the inner portions. The film density of the carbon-containing insulating films is raised in the end portions thereof than in the inner portions.
    Type: Application
    Filed: March 7, 2006
    Publication date: September 21, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Koichi Ohto, Tatsuya Usami
  • Publication number: 20060186549
    Abstract: A first gas including a silicon-containing compound is introduced into a vacuum chamber, to expose a semiconductor substrate placed in the chamber to the first gas atmosphere (silicon processing step). Then the pressure inside the vacuum chamber is reduced to a level lower than the pressure at the time of starting the silicon processing step (depressurizing step). Thereafter, a second gas including a nitrogen-containing compound is introduced into the vacuum chamber, and the semiconductor substrate is irradiated with the second gas plasma (nitrogen plasma step).
    Type: Application
    Filed: February 16, 2006
    Publication date: August 24, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tatsuya Usami, Koichi Ohto, Toshiyuki Takewaki
  • Patent number: 7074698
    Abstract: A method of fabricating a semiconductor device using a PECVD method is provided, which improves the adhesion strength of a deposited dielectric layer to an underlying layer and the reliability of the deposited dielectric layer. After placing a substrate in a chamber, a gas having a thermal conductivity of 0.1 W/mK or greater (e.g., H2 or He) is introduced into the chamber, thereby contacting the gas with the substrate for stabilization of a temperature of the substrate. A desired dielectric layer is deposited on or over the substrate in the chamber using a PECVD method after the step of introducing the gas. As the desired dielectric layer, a dielectric layer having a low dielectric constant, such as a SiCH, SiCHN, or SiOCH layer, is preferably used.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: July 11, 2006
    Assignee: NEC Electronics Corporation
    Inventors: Noboru Morita, Tatsuya Usami, Koichi Ohto, Sadayuki Ohnishi, Koji Arita, Ryohei Kitao, Yoichi Sasaki
  • Publication number: 20060141778
    Abstract: A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.
    Type: Application
    Filed: February 23, 2006
    Publication date: June 29, 2006
    Inventors: Takashi Tonegawa, Koji Arita, Tatsuya Usami, Noboru Morita, Koichi Ohto, Yoichi Sasaki, Sadayuki Ohnishi, Ryohei Kitao
  • Publication number: 20060060975
    Abstract: A technology for inhibiting the dielectric breakdown occurred in a semiconductor device is provided. A semiconductor device comprises a semiconductor substrate (not shown), an interlayer insulating film 102 formed on the semiconductor substrate and a multiple-layered insulating film 140 provided on the interlayer insulating film 102. The semiconductor device comprises an electric conductor, which is provided to extend through the multiple-layered insulating film 140 and includes a Cu film 120 and a barrier metal film 118. The barrier metal film 118 is provided so as to cover side surfaces and a bottom surface of the Cu film 120. This semiconductor device comprises an insulating film 116, which is disposed between the multiple-layered insulating film 140 and the electric conductor (i.e., Cu film 120 and barrier metal film 118).
    Type: Application
    Filed: September 7, 2005
    Publication date: March 23, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tatsuya Usami, Noboru Morita, Koichi Ohto
  • Publication number: 20060038297
    Abstract: Propagation of a crack in a semiconductor device is to be suppressed, thus to protect an element forming region. An interface reinforcing film is provided so as to cover a sidewall of a concave portion that penetrates a SiCN film and a SiOC film formed on a silicon substrate. The interface reinforcing film is integrally and continuously formed with another SiOC film, and includes an air gap.
    Type: Application
    Filed: August 5, 2005
    Publication date: February 23, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tatsuya Usami, Koichi Ohto
  • Publication number: 20050167844
    Abstract: A semiconductor device having improved adhesiveness between films composing an interlayer insulating film is presented by providing multilayered films in the interlayer insulating films having film density distribution, in which the film density is gradually changes. A SiOC film is deposited to a thickness of 300 nm via a plasma CVD process, in which a flow rate of trimethylsilane gas is stepwise increased. In this case, the film density of the deposited SiOC film is gradually decreased by stepwise increasing the flow rate of trimethylsilane gas. Since trimethylsilane contains methyl group, trimethylsilane has more bulky molecular structure in comparison with monosilane or the like. Thus, the film density is decreased by increasing the amount of trimethylsilane in the reactant gas.
    Type: Application
    Filed: December 8, 2004
    Publication date: August 4, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Koichi Ohto, Tatsuya Usami, Yoichi Sasaki
  • Publication number: 20050170633
    Abstract: A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.
    Type: Application
    Filed: February 3, 2005
    Publication date: August 4, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoichi Sasaki, Koichi Ohto, Noboru Morita, Tatsuya Usami, Hidenobu Miyamoto
  • Publication number: 20050159012
    Abstract: In a semiconductor device, an interlevel insulating film formed between a Cu interconnection, formed by damascene, and an upper metal interconnection layer on it has a multilayered structure made up of a Cu diffusion preventive insulating layer and another insulating film. The Cu diffusion preventive insulating layer has a multilayered structure made up of not less than two layers. A method for manufacturing the semiconductor device is also disclosed.
    Type: Application
    Filed: March 1, 2005
    Publication date: July 21, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Koichi Ohto, Takayuki Matsui
  • Patent number: 6879042
    Abstract: In a semiconductor device, an interlevel insulating film formed between a Cu interconnection, formed by damascene, and an upper metal interconnection layer on it has a multilayered structure made up of a Cu diffusion preventive insulating layer and another insulating film. The Cu diffusion preventive insulating layer has a multilayered structure made up of not less than two layers. A method for manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: April 12, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Koichi Ohto, Takayuki Matsui
  • Publication number: 20040266171
    Abstract: In order to provide a manufacturing method of a semiconductor device which can improve the interconnection lifetime, while controlling the increase in resistance thereof, and, in addition, can raise the manufacturing stability; by applying a plasma treatment to the surface of a copper interconnection 17 with a source gas comprising a nitrogen element being used, a copper nitride layer 24 is formed, and thereafter a silicon nitride film 18 is formed. Hereat, under the copper nitride layer 24, a thin copper silicide layer 25 is formed.
    Type: Application
    Filed: July 28, 2004
    Publication date: December 30, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hidemitsu Aoki, Hiroaki Tomimori, Norio Okada, Tatsuya Usami, Koichi Ohto, Takamasa Tanikuni
  • Publication number: 20040183162
    Abstract: A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure having a metal wiring pattern formed therein. The insulating layer structure includes a first SiOCH layer, a second SiOCH layer formed on the first SiOCH layer, and a silicon dioxide (SiO2) layer formed on the second SiOCH layer. The second SiOCH layer features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer, and an oxygen (O) density higher than that of the first SiOCH layer.
    Type: Application
    Filed: January 29, 2004
    Publication date: September 23, 2004
    Applicant: NEC Electronics Corporation
    Inventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Sadayuki Ohnishi, Koji Arita, Ryohei Kitao, Yoichi Sasaki
  • Publication number: 20040185668
    Abstract: A method of fabricating a semiconductor device using a PECVD method is provided, which improves the adhesion strength of a deposited dielectric layer to an underlying layer and the reliability of the deposited dielectric layer. After placing a substrate in a chamber, a gas having a thermal conductivity of 0.1 W/mK or greater (e.g.. H2 or He) is introduced into the chamber, thereby contacting the gas with the substrate for stabilization of a temperature of the substrate. A desired dielectric layer is deposited on or over the substrate in the chamber using a PECVD method after the step of introducing the gas. As the desired dielectric layer, a dielectric layer having a low dielectric constant, such as a SiCH, SiCHN, or SiOCH layer, is preferably used.
    Type: Application
    Filed: January 30, 2004
    Publication date: September 23, 2004
    Applicant: NEC Electronics Corporation
    Inventors: Noboru Morita, Tatsuya Usami, Koichi Ohto, Sadayuki Ohnishi, Koji Arita, Ryohei Kitao, Yoichi Sasaki
  • Patent number: 6787480
    Abstract: In order to provide a manufacturing method of a semiconductor device which can improve the interconnection lifetime, while controlling the increase in resistance thereof, and, in addition, can raise the manufacturing stability; by applying a plasma treatment to the surface of a copper interconnection 17 with a source gas comprising a nitrogen element being used, a copper nitride layer 24 is formed, and thereafter a silicon nitride film 18 is formed. Hereat, under the copper nitride layer 24, a thin copper silicide layer 25 is formed.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: September 7, 2004
    Assignee: NEC Corporation
    Inventors: Hidemitsu Aoki, Hiroaki Tomimori, Norio Okada, Tatsuya Usami, Koichi Ohto, Takamasa Tanikuni
  • Publication number: 20040155342
    Abstract: An object of the present invention is to provide a semiconductor device which comprises a barrier film having a high etching selection ratio of the interlayer insulating film thereto, a good preventive function against the Cu diffusion, a low dielectric constant and excellent adhesiveness to the Cu interconnection and a manufacturing method thereof.
    Type: Application
    Filed: February 2, 2004
    Publication date: August 12, 2004
    Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Tatsuya Usami, Noboru Morita, Koichi Ohto, Kazuhiko Endo
  • Publication number: 20040152334
    Abstract: The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by the reduction in device size, there have arisen strong demands that dielectric constants should be further reduced.
    Type: Application
    Filed: December 30, 2003
    Publication date: August 5, 2004
    Applicants: NEC Electonics Corporation, NEC Corporation
    Inventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Kazuhiko Endo
  • Publication number: 20040046261
    Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.
    Type: Application
    Filed: August 28, 2003
    Publication date: March 11, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Koichi Ohto, Toshiyuki Takewaki, Tatsuya Usami, Nobuyki Yamanishi
  • Publication number: 20040029380
    Abstract: A method for fabricating a semiconductor device wherein an interconnect made of copper overlying a substrate is pretreated at a specified temperature, for example, at 300° C. or less; and a dielectric film is formed on the copper at a temperature higher than that of the pretreatment. In accordance with the present invention, the adhesion between the copper and the dielectric film is improved by conducting the pretreatment of the dielectric film for reducing an oxide layer of the copper surface, and the agglomeration of the copper can be prevented by the pretreatment.
    Type: Application
    Filed: July 21, 2003
    Publication date: February 12, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Koichi Ohto