Abstract: A sustain voltage applying circuit includes a circuit having a sustain pulse generating circuit for generating a sustain pulse of a predetermined waveform and an offset pulse generating circuit for generating an offset pulse higher in peak value than the sustain pulse, the sustain pulse generating circuit and the offset pulse generating circuit being connected in parallel, the offset pulse generating circuit including a first voltage source, a first switching circuit, an inductance component for generating a resonance voltage for the offset pulse generation, and a forward diode for permitting a current supplied to the display electrodes to flow forward so that the resonance voltage is maintained at a higher voltage level than a voltage level of a sustain voltage for a predetermined period of time, the sustain pulse generating circuit including a second voltage and a second switching circuit.

Abstract: A method for driving a plasma display panel is provided in which a wall voltage at an interelectrode between a display electrode and an address electrode is controlled without increasing contrast in preparation for addressing, so that reliability of addressing is improved. As an operation of initialization for controlling the wall voltage of a cell within a screen as a preparation for the addressing, a first blunt wave application is performed for generating discharge only in a previous non-lighted cell that was not lighted in a previous display, and a second blunt wave application is performed for generating discharge in each of the previous non-lighted cell and a previous lighted cell that was lighted in the previous display.

Abstract: A method of driving a PDP including alternately-arranged X and Y electrodes and A electrodes crossing the X and Y electrodes provides a recurring cycle of a resetting period, an addressing period, and a sustaining period. The method includes applying a ramp waveform in the resetting period. Discharge starting threshold voltages between the X and Y electrodes and between the A and Y electrodes are denoted by VtXY and VtAY, respectively. Voltages applied between the X and Y electrodes and between the A and Y electrodes at the trailing edge of the ramp waveform are denoted by VXY and VAY, respectively. An offset voltage of the voltage applied between the A and Y electrodes at the end of the sustaining period is denoted by Vaoff. In such a case, the voltage of a driving waveform for each electrode is set so as to satisfy the relational expression “2 VtAY?VtXY>2VAY?VXY?2Vaoff”.

Abstract: A method for driving a plasma display panel is provided in which initialization is performed securely and the background light emission is reduced. As an operation for the initialization, an obtuse waveform pulse is applied to all cells three times. In the first obtuse waveform pulse application, discharge is generated only in the previously lighted cell, so that the wall voltage thereof approaches the wall voltage in the previously unlighted cell. In the second obtuse waveform pulse application, discharge is generated in the previously lighted cell and in the previously unlighted cell, so that the wall voltage in these cells changes to a value within an appropriate range. In the third obtuse waveform pulse application, discharge is generated in the previously lighted cell and in the previously unlighted cell, so that the wall voltage of these cells changes to a preset value.

Abstract: A method for driving a PDP is provided in which addressing having little influence from operating environment changes is realized without increasing withstand voltage of circuit components, so that a display is stabilized. The method comprises the step of keeping a scan electrode in high impedance state to a power source line over a part or the entire period of a selection waiting period before the scan electrode is biased to a selection potential level.

Abstract: A method for driving a plasma display panel is provided in which a wall voltage at an interelectrode between a display electrode and an address electrode is controlled without increasing contrast in preparation for addressing, so that reliability of addressing is improved. As an operation of initialization for controlling the wall voltage of a cell within a screen as a preparation for the addressing, a first blunt wave application is performed for generating discharge only in a previous non-lighted cell that was not lighted in a previous display, and a second blunt wave application is performed for generating discharge in each of the previous non-lighted cell and a previous lighted cell that was lighted in the previous display.

Abstract: A method of driving a PDP including alternately-arranged X and Y electrodes and A electrodes crossing the X and Y electrodes provides a recurring cycle of a resetting period, an addressing period, and a sustaining period. The method includes applying a ramp waveform in the resetting period. Discharge starting threshold voltages between the X and Y electrodes and between the A and Y electrodes are denoted by VtXY and VtAY, respectively. Voltages applied between the X and Y electrodes and between the A and Y electrodes at the trailing edge of the ramp waveform are denoted by VXY and VAY, respectively. An offset voltage of the voltage applied between the A and Y electrodes at the end of the sustaining period is denoted by Vaoff. In such a case, the voltage of a driving waveform for each electrode is set so as to satisfy the relational expression “2 VtAY−VtXY>2VAY−VXY−2Vaoff”.

Abstract: The present invention provides that a gas discharge panel substrate assembly comprising: electrodes formed on a substrate, a dielectric layer covering the electrodes, and a protective layer covering the dielectric layer and in contact with a discharge space, wherein the protective layer includes MgO and at least one compound selected from the group consisting of an Al compound, a Ti compound, a Y compound, a Zn compound, a Zr compound, a Ta compound and SiC.

Abstract: A method for driving a plasma display panel is provided in which initialization is performed securely and the background light emission is reduced. As an operation for the initialization, an obtuse waveform pulse is applied to all cells three times. In the first obtuse waveform pulse application, discharge is generated only in the previously lighted cell, so that the wall voltage thereof approaches the wall voltage in the previously unlighted cell. In the second obtuse waveform pulse application, discharge is generated in the previously lighted cell and in the previously unlighted cell, so that the wall voltage in these cells changes to a value within an appropriate range. In the third obtuse waveform pulse application, discharge is generated in the previously lighted cell and in the previously unlighted cell, so that the wall voltage of these cells changes to a preset value.

Abstract: A method for setting an applied voltage in a plasma display panel is provided, in which a driving voltage margin is increased. A charge adjustment is performed by generating a discharge for changing a wall charge quantity without changing a polarity of the charging before addressing. In a coordinates space describing the relationship between the effective voltage between the first electrodes and the effective voltage between the second electrodes, a voltage range (Vt closed curve) that can generate a microdischarge for the charge adjustment is determined, and a waveform of an increasing voltage that is applied to the discharge cell is determined in accordance with a Vt closed curve.

Abstract: A method for driving an AC type plasma display panel is provided in which time necessary for addressing can be shortened without deteriorating stability of a display. Before the addressing, a reset process is performed by applying an increasing waveform voltage between a reference potential line and a scan electrode so as to equalize charge in all cells. In the addressing, a selection voltage Vya1 having the same polarity as a final applied voltage Vyr2 in the reset process and an absolute value larger than the voltage Vyr2 by a potential difference &Dgr;Vy is applied between a scan electrode corresponding to a selected row and the reference potential line.

Abstract: A method for driving an AC type plasma display panel is provided in which time necessary for addressing can be shortened without deteriorating stability of a display. Before the addressing, a reset process is performed by applying an increasing waveform voltage between a reference potential line and a scan electrode so as to equalize charge in all cells. In the addressing, a selection voltage Vya1 having the same polarity as a final applied voltage Vyr2 in the reset process and an absolute value larger than the voltage Vyr2 by a potential difference Vy is applied between a scan electrode corresponding to a selected row and the reference potential line.

Abstract: A method for driving a PDP is provided in which addressing having little influence from operating environment changes is realized without increasing withstand voltage of circuit components, so that a display is stabilized. The method comprises the step of keeping a scan electrode in high impedance state to a power source line over a part or the entire period of a selection waiting period before the scan electrode is biased to a selection potential level.

Abstract: A method and device for driving a display panel are provided in which power consumption due to interelectrode capacitance in the addressing period is reduced with less number of components in a driving circuit. Four switches 41-44 are provided for each of plural data electrodes. The four switches 41-44 control open and close of a current path p1 from a bias potential line 81 to the data electrode A, a current path p2 from a capacitor 55 to the data electrode A, a current path p3 from the data electrode A to the capacitor 55, and a current path p4 from the data electrode A to the ground potential line 82.

Abstract: A method and device for driving a display panel are provided in which power consumption due to interelectrode capacitance in the addressing period is reduced with less number of components in a driving circuit. Four switches 41-44 are provided for each of plural data electrodes. The four switches 41-44 control open and close of a current path p1 from a bias potential line 81 to the data electrode A, a current path p2 from a capacitor 55 to the data electrode A, a current path p3 from the data electrode A to the capacitor 55, and a current path p4 from the data electrode A to the ground potential line 82.

Abstract: A method for setting an applied voltage in a plasma display panel is provided, in which a driving voltage margin is increased. A charge adjustment is performed by generating a discharge for changing a wall charge quantity without changing a polarity of the charging before addressing. In a coordinates space describing the relationship between the effective voltage between the first electrodes and the effective voltage between the second electrodes, a voltage range (Vt closed curve) that can generate a microdischarge for the charge adjustment is determined, and a waveform of an increasing voltage that is applied to the discharge cell is determined in accordance with a Vt closed curve.

Abstract: A plasma display panel that can enlarge the voltage margin and can realize a stable display is provided. The plasma display panel includes first and second display electrodes X, Y for generating surface discharge and address electrodes A that cross the display electrodes via a dielectric layer. In the preparation process of the addressing for forming charge distribution corresponding to display contents, charge forming and charge adjusting are performed. The charge forming generates wall voltage having the same polarity at the same kind of interelectrode of all cells constituting the screen, for three kinds of interelectrodes, an interelectrode XY between the display electrodes, an interelectrode XA between the first display electrode and the address electrode, and an interelectrode YA between the second display electrode and the address electrode. The charge adjusting decreases the wall voltage by applying an increasing voltage that increases continuously or step by step.