Abstract: A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order to make a ratio of the switching current and the leakage current constant; a delay observer for observing a delay amount; and a power supply voltage controller for controlling a power supply voltage in order to keep the delay amount in a predetermined range. In the semiconductor integrated circuit device, a process which enables the minimization of an operation power is carried out by controlling the threshold voltage to make the ratio of the switching current and the leakage current constant at a given clock frequency and controlling the power supply voltage to guarantee the operating speed.

Abstract: The present invention provides a pharmaceutical composition which can permit a sparingly water-soluble drug substance to be solubilized or dispersed in a pharmaceutically allowable liquid medium (e.g., fat emulsion, etc.), characterized in that said pharmaceutical composition contains (a) a base (e.g., polyethylene glycol, etc.), (b) a sparingly water-soluble drug substance and (c) a fatty acid or its pharmaceutically allowable salt. The pharmaceutical composition can be mixed with a pharmaceutically allowable liquid medium to produce a pharmaceutical preparation for administration, such as an injectable solution, etc., wherein mixing can be performed for a shortened period of time and the sparingly water-soluble drug substance can be uniformly solubilized or dispersed in a liquid medium.

Abstract: A server load sharing system having a plurality of server load balancers and a relay device. Each balancer includes a module selecting, any one of a plurality of load sharing target servers specified in their group on the basis of the virtual IP address and each allocated a unique IP address, and a module rewriting a virtual IP address of the received forwarding target packet addressed to the virtual IP address into the unique IP address of the selected server, and rewriting a source IP address of the received packet addressed to the virtual IP address into an IP address capable of specifying the other of the first and second links.

Abstract: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

Abstract: When an SRAM cell formed by six transistors is made finer and operated at a lower voltage, it does not operate stably. Because many transistors and control signals are required for stable operation, there is a problem that its component area is increased. An SRAM cell is formed by five transistors. The SRAM cell is formed by an inverter circuit (P1, N1) using a storage node V2 as an input and a storage node V1 as an output, a load transistor P2 connected between a power source VDD and the storage node V2 with using the storage node V1 as an input and the storage node V2 as an output, an access transistor N3 connected between a read bit line RBL and the storage node V1, and an access transistor N4 connected between a write bit line WBL and the storage node V2.

Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a p

Abstract: In a communication system, a first communication apparatus includes: an application data generating unit for generating application data including data at an application level and a priority at the application level; and a lower-level packet generating unit disposed therein for generating a packet by adding to the application data a header including a destination address and a source address at a level lower than the application level. A first relay apparatus includes: a priority identifying unit disposed therein for determining whether or not a priority is set in the application data of the packet received by the first relay apparatus, and thereby identifying a first priority at the application level; and a priority control unit disposed therein for renewing a TOS field value in the header of the packet, the header being at the level lower than the application level, on the basis of the first priority.

Abstract: An information processing system, for processing information obtained from multiple sites that are connected via the Internet 10, includes: a webcrawler 13, for crawling sites, across the Internet 10, which are registered in a registered site DB 11; a metadata DB 12, for storing metadata from which information elements are extracted from content referred to by using a URL; an important information element extraction mechanism 30, for reading information stored in the metadata DB 12, and for extracting important information elements based on the matching level of information elements; an important information element DB 40, for storing the extracted important information elements; and a result display mechanism 41, for visually presenting said stored important information elements.

Abstract: A semiconductor device having SRAM cell units each comprising a pair of driving transistors, a pair of load transistors and a pair of access transistors, in which each of the transistors has a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulting film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; a longitudinal direction of each semiconductor layer extends along a first direction; and between the adjacent SRAM cell units in the first direction, the semiconductor layer in one of the corresponding transistors is located on a center line of the semiconductor layer in the other transistor which center line extends along the first direction.

Abstract: There is provided a semiconductor storage device capable of executing a high-speed read operation without increasing a chip area thereof. The semiconductor storage device includes per-bit sensing circuits 103 each connected to a pair of bit lines (BLT, BLN) and a data output circuit 104 connected to the bit lines BLT from the per-bit sensing circuits, for outputting read data. Each of the per-bit sensing circuits 103 includes a pre-charge circuit for setting the bit line pair to a supply voltage VDD when a bit line pair selection signal YS is inactive, a latch circuit for setting the bit line pair to complementary levels (VDD and GND) according to a read signal when the bit line pair selection signal YS and a sensing circuit activation signal SE are active, and a data write circuit connected to a pair of write data lines (WDT, WDN), for setting one of the bit line pair to a second level (GND) according to write data when the bit line pair selection signal is active.

Abstract: A programmable semiconductor device of the invention includes: processing element unit executing a predetermined operation; input/output connection unit acting as a signal input part and/or a signal output part in processing element unit; interconnecting unit, comprised of a plurality of wires, connecting processing element unit via input/output connection unit; bidirectional repeater unit, arranged between the intersection points of interconnecting unit, performing disconnection, or driving interconnecting unit in the forward direction or in the reverse direction; and interconnection connecting unit, arranged at the intersection point, connecting interconnecting unit at the intersection point.

Abstract: There is provided a semiconductor device comprising an n-type and a p-type field effect transistors, meeting the conditions that in terms of a crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {100} plane substantially orthogonal to the {100} plane, and that in terms of a crystal orientation of the protruding semiconductor region constituting the p-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {110} plane substantially orthogonal to the {100} plane.

Abstract: A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain regions provided in the semiconductor raised portion; an interlayer insulating film provided on a substrate including the transistor; and a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor, wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion and another conductive portion below the interlayer insulating film.

Abstract: There is provided a semiconductor device wherein at least the largest width of a source/drain region is larger than the width of a semiconductor region and the source/drain region has a slope having a width continuously increasing from the uppermost side to the substrate side, and a silicide film is formed in the surface of the slope.

Abstract: A method and apparatus for associating text information with numerical information. A first phrase corresponding to a time period is generated. The first phrase represents a change in first numerical information over the time period. The first numerical information includes time-series data pertaining to a financial index. The text information is retrieved through use of a retrieval condition that includes the first phrase. The first numerical information is retrieved through use of the retrieval condition and the first phrase. The extracted text information and the retrieved first numerical information are outputted in association with each other.

Abstract: An apparatus which manages confidentiality of information. This apparatus includes: a recording unit operable to record information in association with a history of users having accessed the information, or, with access rights defining users able to access the information; a generating unit operable to generate management information indicating whether the information should be managed confidentially from users not permitted to access the information; a selecting unit operable to select, based on the history or access rights, users able to access the information; and a notifying unit operable to notify the selected users of the generated management information in association with identification information of the information.

Abstract: The SRAM cells of a semiconductor storage device each comprise first and second inverter circuits loop-connected with each other to form a hold circuit; two access transistors; and a hold control transistor connected in series with a drive transistor of the second inverter circuit. While the memory cell is not accessed, the hold control transistor causes the first and second inverter circuits to form the loop connected hold circuit for statically holding data. When the memory cell is accessed, the hold control transistor causes the first and second inverter circuits to be disconnected from the loop connection for dynamically holding data, thereby preventing data corruption that would otherwise possible occur due to a read operation. Moreover, a sense amplifier circuit that uses a single bit line to read data from a memory cell is disposed in a space appearing in the memory cell array, thereby effectively using the area.

Abstract: A competition arbitration system in which chances for using a resource of a computer such as a bus or the like among devices are fair is provided. Pulses are sequentially generated periodically from a pulse generating circuit. It is assumed that first device outputted first bus request signal and second device continuously outputted second bus request signal before rising timing of the first pulse. When a bus arbiter outputs a bus grant signal to the first device at the rising timing of the first pulse, the bus master of the first device outputs a bus use acknowledgment signal. Then a use grant inhibiting circuit receives the acknowledgment signal and outputs an inhibition signal for inhibiting use of other devices. Thus, the first device holds the use right of a bus and bus use requests of other devices are reserved.

Abstract: There is provided a semiconductor storage device capable of executing a high-speed read operation without increasing a chip area thereof. The semiconductor storage device includes per-bit sensing circuits 103 each connected to a pair of bit lines (BLT, BLN) and a data output circuit 104 connected to the bit lines BLT from the per-bit sensing circuits, for outputting read data. Each of the per-bit sensing circuits 103 includes a pre-charge circuit for setting the bit line pair to a supply voltage VDD when a bit line pair selection signal YS is inactive, a latch circuit for setting the bit line pair to complementary levels (VDD and GND) according to a read signal when the bit line pair selection signal YS and a sensing circuit activation signal SE are active, and a data write circuit connected to a pair of write data lines (WDT, WDN), for setting one of the bit line pair to a second level (GND) according to write data when the bit line pair selection signal is active.

Abstract: Transition signal control for creating asynchronous timing is provided using a transition signal control circuit, which includes Muller C elements each with an inverter. The control device is constituted by a machine ring including n-stages of transition signal control circuits, a state ring including k-stages of transition signal control circuits, and a synchronous circuit for synchronizing with the machine ring by receiving a vector which is output from the state ring. When the output vector of the state ring is received, the synchronous circuit outputs a vector to the machine ring. The output vector of the machine ring and the output vector of the state ring create timings for controlling the processor, for example, asynchronously, and these timings are input to the instruction decoder, for example.