Patents by Inventor Koichi Toba

Koichi Toba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160372537
    Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventors: Yoshiyuki KAWASHIMA, Koichi TOBA, Yasushi ISHII, Toshikazu MATSUI, Takashi HASHIMOTO
  • Patent number: 9520504
    Abstract: In an MONOS-type memory cell with a split gate structure, short circuit between a selection gate electrode and a memory gate electrode is prevented, and reliability of a semiconductor device is improved. In a MONOS memory having a selection gate electrode and a memory gate electrode that are adjacent to each other and that extend in a first direction, an upper surface of the selection gate electrode in a region except for a shunt portion at an end portion of the selection gate electrode in the first direction is covered with a cap insulating film. The memory gate electrode is terminated on the cap insulating film side with respect to a border between the cap insulating film and an upper surface of the shunt portion exposed from the cap insulating film.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: December 13, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Toba, Hiraku Chakihara, Yoshiyuki Kawashima
  • Patent number: 9461105
    Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: October 4, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Koichi Toba, Yasushi Ishii, Toshikazu Matsui, Takashi Hashimoto
  • Publication number: 20160225902
    Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.
    Type: Application
    Filed: April 7, 2016
    Publication date: August 4, 2016
    Inventors: Koichi TOBA, Hiraku CHAKIHARA, Yoshiyuki KAWASHIMA, Kentaro SAITO, Takashi HASHIMOTO
  • Patent number: 9379127
    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: June 28, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koichi Toba, Yasushi Ishii, Hiraku Chakihara, Kota Funayama, Yoshiyuki Kawashima, Takashi Hashimoto
  • Patent number: 9373630
    Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: June 21, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koichi Toba, Hiraku Chakihara, Yoshiyuki Kawashima, Kentaro Saito, Takashi Hashimoto
  • Publication number: 20160118394
    Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.
    Type: Application
    Filed: January 7, 2016
    Publication date: April 28, 2016
    Inventors: Koichi TOBA, Hiraku CHAKIHARA, Yoshiyuki KAWASHIMA, Kentaro SAITO, Takashi HASHIMOTO
  • Patent number: 9263291
    Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: February 16, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koichi Toba, Hiraku Chakihara, Yoshiyuki Kawashima, Kentaro Saito, Takashi Hashimoto
  • Patent number: 9248658
    Abstract: A liquid storage container includes a liquid storage part, a liquid supply part, a liquid outflow part, and a cover. The liquid storage part stores a liquid. The liquid supply part has a liquid supply port defining an opening by which the liquid is supplied to a liquid jet apparatus from the liquid storage part. The liquid outflow part is made of a porous material. The liquid outflow part is disposed inside of the liquid supply port and allows the liquid to flow out to the liquid jet apparatus from the liquid storage part. The cover includes a sealing part contacting with the liquid supply part and sealing off the liquid supply port, the sealing part and the liquid outflow part defining a space therebetween, and a contact part made of a non-porous material, the contact part contacting with a part of the liquid outflow part.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: February 2, 2016
    Assignee: Seiko Epson Corporation
    Inventors: Tadahiro Mizutani, Koichi Toba, Atsushi Kobayashi
  • Patent number: 9231115
    Abstract: An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed. Of the insulating film, the portion between the lower surface of the memory gate electrode and the upper surface of a semiconductor substrate has silicon oxide films, and a silicon nitride film interposed between the silicon oxide films. Of the insulating film, the portion between a side surface of the control gate electrode and a side surface of the memory gate electrode is formed of a silicon oxide film, and does not have the silicon nitride film.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Koichi Toba
  • Patent number: 9159843
    Abstract: To improve the electric performance and reliability of a semiconductor device. A memory gate electrode of a split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 6a and a silicon film 6b over the metal film 6a. In an upper end part of the metal film 6a, a metal oxide portion 17 is formed by oxidation of a part of the metal film 6a. A control gate electrode of the split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 4a and the silicon film 4b over the metal film 4a.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: October 13, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kentaro Saito, Kazumasa Yanagisawa, Yasushi Ishii, Koichi Toba
  • Publication number: 20150287736
    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film,. and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.
    Type: Application
    Filed: June 19, 2015
    Publication date: October 8, 2015
    Inventors: Koichi Toba, Yasushi Ishii, Hiraku Chakihara, Kota Funayama, Yoshiyuki Kawashima, Takashi Hashimoto
  • Publication number: 20150171160
    Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
    Type: Application
    Filed: March 3, 2015
    Publication date: June 18, 2015
    Inventors: Yoshiyuki KAWASHIMA, Koichi TOBA, Yasushi ISHII, Toshikazu MATSUI, Takashi HASHIMOTO
  • Patent number: 9029931
    Abstract: An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed. Of the insulating film, the portion between the lower surface of the memory gate electrode and the upper surface of a semiconductor substrate has silicon oxide films, and a silicon nitride film interposed between the silicon oxide films. Of the insulating film, the portion between a side surface of the control gate electrode and a side surface of the memory gate electrode is formed of a silicon oxide film, and does not have the silicon nitride film.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Koichi Toba
  • Patent number: 8975678
    Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Koichi Toba, Yasushi Ishii, Toshikazu Matsui, Takashi Hashimoto
  • Patent number: 8969943
    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Toba, Yasushi Ishii, Hiraku Chakihara, Kota Funayama, Yoshiyuki Kawashima, Takashi Hashimoto
  • Publication number: 20150054892
    Abstract: A liquid storage container includes a liquid storage part, a liquid supply part, a liquid outflow part, and a cover. The liquid storage part stores a liquid. The liquid supply part has a liquid supply port defining an opening by which the liquid is supplied to a liquid jet apparatus from the liquid storage part. The liquid outflow part is made of a porous material. The liquid outflow part is disposed inside of the liquid supply port and allows the liquid to flow out to the liquid jet apparatus from the liquid storage part. The cover includes a sealing part contacting with the liquid supply part and sealing off the liquid supply port, the sealing part and the liquid outflow part defining a space therebetween, and a contact part made of a non-porous material, the contact part contacting with a part of the liquid outflow part.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 26, 2015
    Inventors: Tadahiro MIZUTANI, Koichi TOBA, Atsushi KOBAYASHI
  • Publication number: 20140302668
    Abstract: An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed. Of the insulating film, the portion between the lower surface of the memory gate electrode and the upper surface of a semiconductor substrate has silicon oxide films, and a silicon nitride film interposed between the silicon oxide films. Of the insulating film, the portion between a side surface of the control gate electrode and a side surface of the memory gate electrode is formed of a silicon oxide film, and does not have the silicon nitride film.
    Type: Application
    Filed: June 18, 2014
    Publication date: October 9, 2014
    Inventors: Yoshiyuki KAWASHIMA, Koichi TOBA
  • Publication number: 20140239378
    Abstract: In an MONOS-type memory cell with a split gate structure, short circuit between a selection gate electrode and a memory gate electrode is prevented, and reliability of a semiconductor device is improved. In a MONOS memory having a selection gate electrode and a memory gate electrode that are adjacent to each other and that extend in a first direction, an upper surface of the selection gate electrode in a region except for a shunt portion at an end portion of the selection gate electrode in the first direction is covered with a cap insulating film. The memory gate electrode is terminated on the cap insulating film side with respect to a border between the cap insulating film and an upper surface of the shunt portion exposed from the cap insulating film.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 28, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Koichi Toba, Hiraku Chakihara, Yoshiyuki Kawashima
  • Patent number: D769966
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: October 25, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Tadahiro Mizutani, Koichi Toba, Atsushi Kobayashi