Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.

Abstract: In an embodiment, a processor includes a binary translation (BT) container having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache, a host entity logic to manage the BT container and to identify the first code segment, and protection logic to isolate the BT container from a software stack. In this way, the BT container is configured to be transparent to the software stack. Other embodiments are described and claimed.

Abstract: Embodiments of techniques and systems associated with binary translation (BT) in computing systems are disclosed. In some embodiments, a BT task to be processed may be identified. The BT task may be associated with a set of code and may be identified during execution of the set of code on a first processing core of the computing device. The BT task may be queued in a queue accessible to a second processing core of the computing device, the second processing core being different from the first processing core. In response to a determination that the second processing core is in an idle state or has received an instruction through an operating system to enter an idle state, at least some of the BT task may be processed using the second processing core. Other embodiments may be described and/or claimed.

Abstract: In an embodiment, a processor includes a binary translation engine to receive a code segment, to generate a binary translation of the code segment, and to store the binary translation in a translation cache, where the binary translation includes at least one policy check routine to be executed during execution of the binary translation on behalf of a security agent. Other embodiments are described and claimed.

Abstract: This disclosure is directed to binary translator driven program state relocation. In general, a device may protect vulnerable program functions by setting them as non-executable. If an attempt is made to execute a protected program function, the program may trap to a binary translator in the device that may be configured to relocate program state from what has already been established (e.g., on a stack register). Program state may include resources (e.g., memory locations) used by the program during the course of execution. The binary translator may then translate the program into an executable form based on the relocated program state, and may be executed accordingly. Intruding code that attempts to overcome normal program execution and implement hostile operations (e.g., based the program state that is reflected in the stack register) will not function as intended since the relocated program state will cause unexpected results.

Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Abstract: In a bogie frame, a lateral beam disposed in the left-right direction which is the direction in which the rail ties extend is joined to left and right side beams arranged so as to extend in the front-rear direction which is the direction in which the rails extend. The lateral beam has a flat shape having a width in the front-rear direction greater than the thickness thereof in the top-bottom direction, and the lateral beam is provided with left and right joining sections joined to the side beams, and also with an intermediate section sandwiched between the left and right joining sections. The width of the intermediate section in the front-rear direction is greater than the width of the joining sections in the front-rear direction. A through-hole is formed in the intermediate section.

Abstract: Operating system virtual memory management for hardware transactional memory. A system includes an operating system deciding to unmap a first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.

Abstract: An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code for execution on the ASMP is analyzed and a determination is made as to whether to allow the program code, or a code segment thereof to execute on a first core natively or to use binary translation on the code and execute the translated code on a second core which consumes less power than the first core during execution.

Abstract: A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.

Abstract: A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution.

Abstract: In a driving support apparatus for a vehicle, when a driver indicates the intension to turn by turning a turn signal switch on, vehicles traveling on a lane to which the driver intends to turn is detected based on images captured by monitoring cameras, a space to cut into between the vehicles is calculated, an entry start time of a subject vehicle is obtained based on a speed difference between a speed of the subject vehicle and a moving speed of the space to cut into, and, when the entry start time is reached, voice guidance instructing to start turning is output from an instruction unit.

Abstract: An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.

Abstract: A torque limiting device includes: a clutch disc clamp plate 17 having a surface area 13 where the surface and the outer area surface of the flywheel press or come in contact with each other, and is provided with an opening 16 at the center middle part of the clutch disc clamp plate 17 so that a concave space 14 is formed between the clutch disc clamp plate 17 and the fly wheel 2 when the clutch disc clamp plate 17 is fastened to the fly wheel 2; a clutch disc 18 fitted in the concave space, and connected to the driven apparatus; a clutch pressing plate 22 fitted between the clutch disc 18 and the fly wheel 2; and, at least one pressing means fitted to and in the flywheel 2 and presses the clutch pressing plate 22 in a surface contact condition.

Abstract: A method includes receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread.

Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Abstract: For generating photo albums on events such as weddings, the photo albums can always be generated in the same quality. A professional photographer photographs the bride and groom on a wedding. Images are read from a developed film and stored in a file server. A template used for generating a photo album is added with composition information representing composition of images to be inserted in image insertion areas therein. When an operator selects one of the images to be inserted in any one of the image insertion areas with reference to an editing screen having a catalog display field and a template display field, processing information representing a magnification ratio and/or a trimming position is generated based on the composition information so that the selected image has the composition appropriate for the image insertion area. The selected image is processed according to the processing information.

Abstract: A sheet skew feed correcting apparatus is provided which includes: a driving rotation member that is driven to rotate; a first driven rotation member that is pressure contacted against the driving rotation member; a first holder rotatably holding the first driven rotation member; a second driven rotation member that is pressure contacted against the driving rotation member; a second holder rotatably holding the second driven rotation member; and a shutter portion with which a leading end of a sheet comes into contact for skew feed correction, the shutter portion moving pivotally with one end portion thereof supported by the first holder and another end portion thereof supported by the second holder; wherein the shutter portion has abutting portions with which the leading end comes into contact, and a coupling portion extending so as to couple the abutting portions together between the first and the second driven rotation members.

Abstract: In a bogie frame, a lateral beam disposed in the left-right direction which is the direction in which the rail ties extend is joined to left and right side beams arranged so as to extend in the front-rear direction which is the direction in which the rails extend. The lateral beam has a flat shape having a width in the front-rear direction greater than the thickness thereof in the top-bottom direction, and the lateral beam is provided with left and right joining sections joined to the side beams, and also with an intermediate section sandwiched between the left and right joining sections. The width of the intermediate section in the front-rear direction is greater than the width of the joining sections in the front-rear direction. A through-hole is formed in the intermediate section.