Abstract: For generating photo albums on events such as weddings, the photo albums can always be generated in the same quality. A professional photographer photographs the bride and groom on a wedding. Images are read from a developed film and stored in a file server. A template used for generating a photo album is added with composition information representing composition of images to be inserted in image insertion areas therein. When an operator selects one of the images to be inserted in any one of the image insertion areas with reference to an editing screen having a catalog display field and a template display field, processing information representing a magnification ratio and/or a trimming position is generated based on the composition information so that the selected image has the composition appropriate for the image insertion area. The selected image is processed according to the processing information.

Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.

Abstract: Power consumption of current sources in an amplifier circuit is reduced even during amplifier operation while keeping linearity of an output signal. The amplifier circuit is suitable for use in a signal generator that provides an output signal previously set by a user and having a known level. Positive and negative current sources receive an input voltage Vi depending on an output voltage Vo. An output resistor derives the output voltage Vo from currents provided by the positive and negative current sources. A variable bias generation circuit produces positive and negative bias voltages applied to the positive and negative current sources wherein the positive and negative bias voltages are set while the linearity of the output voltage is maintains using the known output level information.

Abstract: A system and method for injecting hardware errors into a microprocessor system is described. In one embodiment, a software interface between system software and system firmware is established. Software test and debug for software error handlers may thus be supported. The software interface may support both a query mode call and a seed mode call. When a query mode call is issued, it may request whether or not the system firmware and hardware support the injection of a specified kind of error. A return from this call may be used to make a list of supported errors for injection. When a seed mode call is issued, the corresponding error may be injected into the hardware.

Abstract: When a photo album for an event such as a wedding ceremony is generated, images to be inserted in image insertion areas in a template can be selected easily. A professional photographer photographs a bride and groom on the wedding day and obtains a plurality of images. Characteristic quantities of scenes represented by the images are calculated, and the images are classified in image groups of respective scenes. The scenes, image groups and image insertion areas of the template for album are related to each other. An event bar is displayed on an editing screen. When a desired scene button is selected, a catalog of images of an image group corresponding to the scene represented by the selected scene button, and the image insertion areas of the template are displayed on the editing screen.

Abstract: Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.

Abstract: Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.

Abstract: An object is to provide a work vehicle whose drive portion can be downsized.

Abstract: In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.

Abstract: In a method for switching to a spare memory module during runtime, a processing system determines that utilization of an active memory module in the processing system should be discontinued. The processing system may then activate a mirror copy mode that causes a memory controller in the processing system to copy data from the active memory module to the spare memory module when the data is accessed in the active memory module. An operating system (OS) in the processing system may then access data in the active memory module to cause the memory controller to copy data from the active memory module to the spare memory module. The processing system may then reconfigure the memory controller to direct reads and writes to the spare memory module instead of the active memory module. Other embodiments are described and claimed.

Abstract: A method for managing virtual memory addresses includes associating a guest identifier (ID) with a virtual machine accessing a virtual memory address. A physical memory address is retrieved corresponding to the virtual memory address utilizing the guest ID. Other embodiments are described and claimed.

Abstract: Use of data poisoning techniques may permit proactive operating system recovery without needing to always bringing down the operating system when uncorrectable errors are encountered.

Abstract: Embodiments described herein disclose a system for enabling emulation of a MIMD ISA extension which supports user-level sequencer management and control, and a set of privileged code executed by both operating system managed sequencers and application managed sequencers, including different sets of persistent per-CPU and per-thread data. In one embodiment, a lightweight code layer executes beneath the operating system. This code layer is invoked in response to particular monitored events, such as the need for communication between an operating system managed sequencer and an application managed sequencer. Control is transferred to this code layer, for execution of special operations, after which control returns back to originally executing code. The code layer is normally dormant and can be invoked at any time when either a user application or the operating system is executing.

Abstract: The invention provides a semiconductor memory device which achieves memory size reduction. This memory is formed on a surface of a p-type silicon substrate, and includes an n-type impurity region serving as a cathode of a diode included in a memory cell and a word, a plurality of p-type impurity regions formed on a surface of the n-type impurity region at predetermined intervals and each serving as an anode of the diode, a bit line formed on the p-type silicon substrate and connected with the p-type impurity region, and a wiring layer provided in a lower layer than the bit line and connected with the n-type impurity region at predetermined intervals.

Abstract: When a photo album is generated of an event such as wedding, images to be inserted in image insertion areas in a template can be selected easily. A professional photographer photographs the bride and groom on the day of wedding, and obtains image data sets. An editing screen has a catalog display field and a template display field. The image data sets are classified into scenes in the event, and correspondence information representing correspondence between the scenes in the event, the classified image data sets, and pages in the template is generated with reference to a table relating the scenes to the pages. A catalog of the image data sets classified into the scene corresponding to a specified one of the pages is displayed in the editing screen with reference to the correspondence information.

Abstract: A processing system may include an operating system (OS) and one or more specialized error handling modules to be registered with the OS after the processing system is powered on. The OS may also include a master policy module. The specialized error handling module may collect error data from a component of the processing system, and may generate abstracted error data, based at least in part on the collected error data. The master policy module may determine a recovery action to be taken, based at least in part on the abstracted error data. The OS may also include an error collection routine that calls one or more specialized error handling modules in response to detecting a hardware error. The error collection routine may also retrieve information from firmware in response to detecting the hardware error. Other embodiments are described and claimed.

Abstract: Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.

Abstract: Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.

Abstract: An RTP packet generating unit 11 packetizes data into packets, and adds identification information to the header of each of the packets, the identification information identifying each of the packets. An RTP packet encrypting unit 13 divides data included in each of the generated packets into blocks, and encrypts the data included in each of the packets on a block-by-block basis using an encryption key which an encryption key sharing unit 12 shares with a receiving client in such a manner that, when encrypting a first block of the data, the packet encrypting unit encrypts it using the identification information for identifying each of the packets, which is contained, as an initial vector, in the header of each of the packets, and, when encrypting each subsequent block of the data, encrypts it according to an encryption method which uses an immediately-previously-encrypted block.

Abstract: Embodiments of memory management in a multiprocessor system are disclosed. Embodiments include a system and method for maintaining translation lookaside buffer (TLB) consistency or coherency in a multiprocessor system. A coalescing component receives from a host system a list of TLB pages to be invalidated or purged. The coalescing component uses information of the TLB invalidation broadcast mechanism in use by a processor in the multiprocessor system to evaluate the list of TLB pages. The coalescing component generates a single TLB invalidation message with a variable invalidation range to cover multiple TLB pages of the list or the entire list of TLB pages to be invalidated, and the invalidation message is used to invalidate multiple TLB pages on multiple processors of the host system. Other embodiments are described and claimed.