Abstract: A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

Abstract: A neural network device includes internal data input lines, internal data output lines, coupling elements provided at the connections of the internal data input lines and the internal data output lines, word lines each for selecting one row of coupling elements. The coupling elements couple, with specific programmable coupling strengths, the associated internal data input lines to the associated internal data output lines. In a program mode, the internal data output lines serve as signal lines for transmitting the coupling strength information.

Abstract: A semiconductor neural network includes a coupling matrix having coupling elements arranged in a matrix which couple with specific coupling strengths internal data input lines to internal data output lines. The internal data output lines are divided into groups. The neural network further comprises weighting addition circuits provided corresponding to the groups of the internal data output lines. A weighting addition circuit includes weighing elements for adding weights to signals on the internal data output lines in the corresponding group and outputting the weighted signals, and an addition circuit for outputting a total sum of the outputs of those weighting elements.

Abstract: In a dynamic random access memory (DRAM) having a sense amplifier of complementary metal oxide semiconductor (CMOS) type, switching transistors are provided for setting the bit line potential and the potential of the sense amplifier driving signal line at the same potential, namely, a half of the voltage applied to the bit line in writing "H", during the bit line equalizing period.

Abstract: In a metal-oxide semiconductor (MOS) dynamic formed on a semiconductor substrate, data nodes of a first flip-flop are connected to a first pair of folded bit lines. Its power supply node is connected through a switch to a first power supply (Vss). Data nodes of a second flip-flop are connected to a second pair of folded bit lines. Its power supply node is connected through a switch to the first power supply (Vss). A power supply node of a third flip-flop is connected through a switch to a second power supply (Vcc). Data nodes of the third flip-flop are coupled through a first pair of transfer gates to the first pair of the folded bit lines, and through a second pair of transfer gates to the second pair of the folded bit lines. Coupling the first to the third flip-flops forms a first sense amplifier and coupling the second to the third flip-flops forms a second sense amplifier.

Abstract: A semiconductor memory device having a folded bit line structure (16a, 16b), in which a field oxide film (2) is formed on both sides of a channel region (11) of a transfer gate, a groove isolation region 12 for defining a memory cell region is formed to surround the field oxide film 2, and the side walls of the groove isolation region 12 include a memory cell utilized as a capacitor for storing charges as information.

Abstract: A neural circuit device modeled on vital cells includes a plurality of first signal lines to which signals to be computed are transferred, a plurality of amplifiers serving as the bodies of the vital cells, a plurality of second signal lines arranged to intersect with the first signal lines in correspondence to the respective amplifiers, and a plurality of coupling elements provided in crossings between the first and second signal lines.

Abstract: A semiconductor neural network includes a plurality of data input line pairs to which complementary input data pairs are transmitted respectively, data output line pairs respectively deriving complementary output data pairs and a plurality of coupling elements arranged at respective crosspoints of the data input lines and the data output lines. The coupling elements are programmable in states, and couple corresponding data output lines and corresponding data input lines in accordance with the programmed states thereof. Differential amplifiers formed by cross-coupled inverting amplifiers are provided in order to detect potentials on the data output lines. The differential amplifiers are provided for respective ones of the data output line pairs.

Abstract: In a memory cell comprising a data cell array and a parity cell array, an error checking.multidot.correcting circuit is connected to each of the arrays through a selector. The selector is constituted by transistors connected to each of the bit lines in the memory cell. The number of circuit elements constituting the error checking.multidot.correcting circuit corresponds to one-half of the number of the bit line pairs included in the data cell array and the parity cell array. In an error correcting mode, half of the data appeared on the bit line pairs in data cell array and the parity cell array are transferred to the error checking.multidot.correcting circuit by the selector, so that the errors are corrected. Thereafter, the data of the remaining half of the bit line pairs are processed in the same manner. Therefore, the number of circuit elements of the error checking.multidot.correcting circuit can be reduced compared with the prior art, improving the degree of integration of the device.

Abstract: In a semiconductor memory device having an error correcting circuit, a pair of bit lines and inverted bit lines are connected to the inputs of first and second inverting amplitude circuits through a first and second N channel MOS transistors, respectively, and the output of the first inverting amplitude circuit is connected to the bit line through a third transistor and the output of the second inverting amplitude circuit is connected to the inverted bit line through a fourth transistor. When an error of information of any bit line pair is detected by an error detecting circuit, the first and second N channel MOS transistors are turned off and each bit line pair is separated from the input of the first and second inverting amplitude circuits and, as a result, information of a bit line pair is rewritten by the output of the first and second inverting amplitude circuits.

Abstract: A semiconductor neural network constructed in accordance with models of vital nerve cells has photosensitive elements as coupling elements providing degrees of coupling between neurons which are modeled vital nerve cells. The conductance values of the photosensitive elements can be set by light. Due to such structure, not only the degrees of coupling of all the coupling elements can be simultaneously programmed but signal lines for programming the degrees of coupling can be eliminated in the network, whereby a semiconductor neural network having a high degree of integration can be implemented without additional complicating fabrication steps.

Abstract: In a dynamic random access semiconductor memory device comprising a sense amplifier and two pairs of bit lines sharing the sense amplifiers, each of the bit lines having a plurality of memory cells connected thereto, when a memory cell connected to one of the bit-line pairs is selected, the memory cells connected to the other bit-line pair are not connected to the sense amplifier, and, during a refresh cycle for rewriting data into a selected memory cell connected to a bit line of one of the bit-line pairs, the bit lines of the other bit-line pair are disconnected from the sense amplifier.

Abstract: A semiconductor memory device having a memory cell array of a folded bit line configuration comprises memory cells, two each of which are formed to share a contact hole and surrounded by an isolation trench, and data charge storage capacitance formed on the entire sidewall of the isolation trench except a part of the isolation trench where an isolation oxide film is formed on the sidewall of the isolation trench. The isolation oxide film separates the two memory cells from each other. One word line passes through a region for one bit memory cell, and two bit lines pass through a region for one bit memory cell.

Abstract: A grooved separating region 112 having information electric charge storing capacitances C.sub.P formed on side surfaces thereof is formed to extend the region between the adjacent word line 107 in parallel with the word line 107. As a result, the grooved separating region 112 does not contact the channel region 111 of the gate transistors and does not intersect the word line 107.

Abstract: A dynamic random access memory (DRAM) comprises a divided plurality of memory array blocks. Each memory array block comprises a memory array having memory cells and a sense amplifier. In refresh operation, activating signals for activating each of the sense amplifiers are outputted. The output timings of the activating signals are different from each other, so that each of the sense amplifiers are activated at different timings. Consequently, a peak value of the current consumed by the activation of the sense amplifiers can be reduced.

Abstract: A first impurity region is formed on the inner surface of a trench formed on the major surface of a semiconductor substrate. The trench is filled with a vertical portion of a first electric conductor having a reversed L-shaped cross section through an insulating film. A first transistor having a first impurity region serving as a source/drain region is formed on the semiconductor substrate. A second impurity region serving as a source/drain region of a second transistor is formed on the major surface of the semiconductor substrate and spaced from the trench. A second electric conductor having a reversed L-shaped cross section for connecting the vertical portion to the second impurity region is formed, and a horizontal portion of the second electric conductor is formed to be stacked on a horizontal portion of the first electric conductor with an insulating film formed therebetween.

Abstract: A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switches are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected to one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

Abstract: In a semiconductor memory device of a redundancy configuration having lines (rows or columns) of main memory cells and a line of spare memory cells made to substitute a defective line responsive to the address of the defective line, a comparator compares an address input to the memory device, with the address of the defective line which has been programmed in it, and a spare line selector selects the spare line when the input address is found to coincide with the programmed address. A line decoder is responsive to the input address for selecting one of the lines of the normal memory cells, and is inactivated by the output of the comparator when the input address is found to coincide with the programmed address. An input address to the line decoder is applied before the same input address is applied to the comparator.

Abstract: A memory cell array is divided into two groups, one bit line of a pair of bit lines is connected to corresponding memory cells in the first group of the memory cell array, and the other bit line thereof is connected to corresponding memory cells in the second group of the memory cell array.

Abstract: A DRAM of a partially activating system, in which, in an active cycle, sense amplifiers (91a, 91b) are inactivated and the potential on each pair of bit lines (BLA1, BLA1, BLA2, BLA2) is equalized early in the active cycle only for a subarray to be accessed while the potential is not equalized and the sense amplifiers are kept to be activated for a subarray not to be accessed. At the time of an inactive cycle, all the sense amplifiers (91a, 91b) are activated, and the bit lines (BLA1, BLA1, BLA2, BLA2) in the memory cell array are at an "H" or "L" level depending on information read out in the previous active cycle.