Abstract: A compiler compiling a source code and is implemented in a plurality of processor cores includes a parallel loop processing detection unit configured to detect from the source code a loop processing code for execution of an internal processing operation for a given number of repeating times, and an independent parallel loop processing code in the internal processing operation performed for each repetition to be concurrently processed, and a dynamic parallel conversion unit configured to generate a control core code for control of the number of repeating times in the parallel loop processing code and a parallel processing code for changing the number of repeating times corresponding to the control from the control core code.

Abstract: An information processing system includes a CPU that is connected to a bus; a device that is connected to the bus; a memory that is accessed by the CPU or the device; and a power mode control circuit that sets a power consumption mode. The power mode control circuit sets the power consumption mode based on first information that indicates a cache hit or a cache miss of a cache memory in the CPU and second information that indicates an activated state or a non-activated state of the device.

Abstract: An information processing apparatus includes a memory unit having numbers each specifying an output order and a data memory area corresponding to each number; a setting unit that sets in each data memory area correlating an execution order of a thread with a number specifying the output order, a storage location for a value of a common variable of the thread among threads receiving write requests for the value or the common variable; a first storing unit that stores to the data memory area set for each thread, the value of the common variable for the thread of the execution order corresponding to the number specifying the output order of the data memory area; and a second storing unit that upon completion of ail the threads and In the output order, reads-out each value of the common variable stored to the data memory areas and overwrites a specific storage location.

Abstract: A multi-core processor system includes a given core among multiple cores, wherein the given core is configured to detect execution of a process by the cores; and generate upon detecting the execution of the process, a specific thread that saves state information indicating an executed state of the process and an executed state of each thread to be monitored of the process.

Abstract: A fuel cell system includes: a fuel cell; a secondary cell that receives and stores surplus power by which output of the fuel cell is greater than power demanded of the system if the output is so, and that compensates for shortfall by which the output of the fuel cell is less than the power demanded of the system if the output is so; a voltage measurement portion that measures voltage of the fuel cell; a current measurement portion that measures current of the fuel cell; and a control portion that performs a control such that the voltage of the fuel cell does not exceed or equal a pre-set high-potential avoidance voltage. If a current-voltage characteristic of the fuel cell declines by at least a pre-determined amount from an early-period level, the control portion re-sets the high-potential avoidance voltage to a value that is smaller than an early-period set value.

Abstract: A hierarchical multi-core processor includes a core group for each hierarchy of a hierarchy group constituting a series of communication functions divided according to communication protocol, where a first core group of a given hierarchy among the hierarchy group is connected to a second core group of another hierarchy constituting a first communication function to be executed following a second communication function of the given hierarchy.

Abstract: A multi-core processor system includes multiple cores; shared memory accessed by the cores; and an arbiter circuit that arbitrates contention of right to access the shared memory by the cores. Each of the cores is configured to acquire for the core, a measured speed of access to the shared memory; calculate for the core, a response performance based on the measured speed of access and a theoretical speed of access for the core; calculate for the cores and based on the response performance calculated for each of the cores, ratios of access rights to access the shared memory, the ratios being calculated such that a ratio of access rights for a given core is larger than a ratio of access rights for another core whose response performance is higher than that of the given core; and notify the arbiter circuit of the calculated ratios of access rights.

Abstract: A multicore processor system includes a processor configured to detect any among a switching process and an assignment process of applications in a multicore processor; acquire upon detecting any among the switching process and the assignment process, a priority level concerning execution of each application assigned to each core of the multicore processor and number of accesses of a shared resource shared by the multicore processor; determine an access ratio of an application whose priority level is highest to each of application remaining after excluding the application whose priority level is highest, among the assigned applications, by comparing the number of accesses by each remaining application and the number of accesses by the application whose priority level is highest; notify an arbiter circuit of the determined access ratios; and arbitrate using the arbiter circuit, the access of the shared resource by the multicore processor, based on the access ratios.

Abstract: A multi-core processor system includes a given core configured to switch at a prescribed switching period, threads assigned to the given core; identify whether the given core has switched threads at a period exceeding the prescribed switching period; correct the prescribed switching period into a shorter switching period, based on a difference of an actual switching period at which the threads have been switched by the given core and the prescribed switching period; and set the corrected switching period as the prescribed switching period.

Abstract: A multicore processor system having multiple cores, includes processors configured to measure bandwidth of a network; compare the measured bandwidth and a given threshold; determine among the cores and based on an obtained comparison result, a core adjustment number by which the number of cores executing a given process related to data communicated through the network is adjusted; calculate the number of executing cores after adjustment by the core adjustment number and based on the number of cores executing the given process before the adjustment and the determined core adjustment number; specify a core executing the given process among the cores and based on the calculated number of executing cores after the adjustment; and distribute the communicated data to the specified core executing the given process.

Abstract: A generating method is executed by a processor. The method includes executing simulation using a simulation model expressing a processor model, a memory model to which the processor model is accessible, and a load source that accesses the memory model according to an access contention rate, to obtain an index value for performance of the processor model, for each access contention rate; and saving to a memory area and as contention characteristics information, the index value for each access contention rate.

Abstract: A multicore processor system includes a processor configured to detect, among cores that have booted with an old boot program in the multicore processor, a core to which no process is assigned; change upon detecting a core to which no process is assigned, a reference area from a storage area for the old boot program to a storage area for a new boot program; and notify the core to which no process is assigned of a reboot instruction specifying the reference area after the change.

Abstract: A software control device includes a processor configured to determine whether starting software and running software are accessing the same common resource; and control the running software to be temporarily suspended upon determining that the starting software and the running software are accessing the same common resource.

Abstract: A multi-core processor system has a first core executing an OS and multiple applications, and a second core to which a first thread of the applications is assigned. The multi-core processor system includes a processor configured to receive from the first core, an interrupt signal specifying an event that has occurred with an application among the applications, determine whether the event specified by the received interrupt signal is any one among a start event for exclusion and a start event for synchronization for the first thread currently under execution by the second core, save from the second core, the first thread currently under execution, upon determining the specified event to be a start event, and assign a second thread different from the saved first thread and among a group of execution-awaiting threads of the applications, as a thread to be executed by the second core.

Abstract: A multi-core processor system includes a multi-core processor and a storage apparatus storing for each application, a reliability level related to operation, where a given core accesses the storage apparatus and is configured to extract from the storage apparatus, the reliability level for a given application that invokes a given thread; judge based on the extracted reliability level and a specified threshold, whether the given application is an application of high reliability; identify, in the multi-core processor, a core that has not been allocated a thread of an application of low reliability, when judging that the given application is an application of high reliability, and identify in the multi-core processor, a core that has not been allocated a thread of an application of high reliability, when judging that the given application is an application of low reliability; and give to the identified core, an invocation instruction for the given thread.

Abstract: A multi-core processor system includes multiple cores and memory accessible from the cores, where a given core is configured to detect among the cores, first cores having a highest execution priority level; identify among the detected first cores, a second core that caused access conflict of the memory; and control a third core that is among the cores, excluding the first cores and the identified second core, the third core being controlled to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.

Abstract: An update method is executed by a processor that downloads a new version of a file concerning a library in an operating system and deletes an old version of the file. The update method includes detecting presence of the new version of the file; creating, when the new version of the file is detected, a second node that specifies a second storage area that is a different area from a first storage area for the old version of the file that is specified by a first node; checking, when the new version of the file is downloaded to the second storage area, whether the old version of the file is in use; and giving notification of an instruction to delete the first node and the old version of the file, when the old version of the file is confirmed at the checking to not be in use.

Abstract: A computer is caused to function as a parsing unit, a macroblocking analyzing unit, a junction-node restructuring unit, an identical portion merging/restructuring unit, a similar portion merging/restructuring unit, and an intermediate language restructuring unit. The parsing unit performs syntax analysis of a source code. The macroblocking analyzing unit segments the program written in the source code into blocks and appends a virtual portion representing a unique number in a statement, to a number for identifying a variable for the statement in each block to virtualize a calculation pattern. The junction-node restructuring unit extracts a node directly related to a subroutine block. The identical portion merging/restructuring unit merges pre-processing together and post-processing together for a subroutine called up at a multiple portions in the program. The similar portion merging/restructuring unit integrates subroutines having similar structures into a related subroutine.

Abstract: An information processing system includes a first apparatus including a position information transmission unit to transmit information on the position of the first apparatus; and a second apparatus including, a position information acquisition unit to acquire a position of the second apparatus; a position information receiving unit to receive the information on the position of the first apparatus; a relative-position information acquisition unit to acquire relative-position information of the second and the first apparatus on the basis of the information on the position of the second and the first apparatus; and a control unit to control a coupling mode of the second and the first apparatus on the basis of the relative-position information.

Abstract: A heat insulating member is sandwiched by a first separator and a second separator. The heat insulating member functions as a heat insulating layer to prevent the temperature decrease of electricity generating cells. A first impurity removal flow path is formed in the space enclosed by the grooves on the surface of the second separator and a partition plate. A second impurity removal flow path is formed in the space enclosed by the grooves on the surface of a third separator and the partition plate. The impurity removal flow paths function as filters to remove the impurities contained in the reaction gases. A terminal functions as a current collecting layer to collect the electricity generated in the electricity generating cells.