Abstract: A computer-readable recording medium stores a program that causes a computer capable of accessing a multicore processor equipped with volatile memories and a plurality of cores accessing the volatile memories, to execute a data restoration process. The data restoration process includes detecting a suspend instruction to any one of the cores in the multicore processor; and restoring, when the suspend instruction is detected, data stored in a volatile memory accessed by a core receiving the suspend instruction, the data being restored in a shared memory accessed by the cores in operation and based on parity data stored in the volatile memories accessed by the cores in operation other than the core receiving the suspend instruction.

Abstract: A multi-core processor system includes a core configured to detect that among cores different from a specific core executing a specific process, a given software different from specific software having a function equivalent to the specific process, is under execution; extract, from a database storing required computing capacities for the plural software and upon detecting that a given software is under execution, requirement values indicating the required computing capacity of the specific software and of the given software; judge for each the cores, whether a sum of the required computing capacities of the specific software and the software is at most a computing capacity value of the core; assign the specific software to a core for which the sum of the required computing capacities is judged to be at most the computing capacity value of the core; and suspend the specific core, upon assigning the specific software to the core.

Abstract: A communication device has: a sensor configured to output sensing data; a count signal communication part configured to count a count signal received from a control device directly or via another communication device and transmit the counted count signal and to store a value of the received count signal; and a data communication part configured to transmit the sensing data outputted by the sensor or the sensing data received from another communication device, in correspondence with the stored value of the count signal.

Abstract: A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.

Abstract: A data processing apparatus that is installed in plural in an installation area and processes data of each installation site, includes a processor that based on a combination of identification information included in calibration information respectively transmitted by calibration nodes and self-identification generation information that is included in the calibration information and for identifying the data processing apparatus among the plural data processing apparatuses, generates self-identification information; a memory device that retains the self-identification information; and a wireless communications circuit that receives the calibration information from the calibration nodes and performs transmission and reception of the data with an adjacent data processing apparatus provided in the installation area.

Abstract: A position estimation apparatus acquires, for base devices, the number of hops from a target sensor node to a base device. The position estimation apparatus calculates, for each base device, a distribution of estimated distances corresponding to the total hops, based on the number of hops and a distribution of estimated distances stored in a storage device. The position estimation apparatus calculates, for each base device, a distribution of estimated positions within a given region, based on the distribution of estimated distances, information concerning a range of the given region, and information concerning a position of the base device. The position estimation apparatus calculates an index that indicates a probability of a position of the target sensor node within the given region, based on the sum of distributions of estimated positions concerning the base stations.

Abstract: There is disclosed a fuel cell in which an insulating material is disposed, whereby the thermal diffusion of the inside and outside of a fuel cell can be suppressed to suppress the deterioration of the performance of the fuel cell due to a temperature drop. Moreover, the physical properties of the insulating material are specified, whereby appropriate insulating properties required in the fuel cell can be obtained, and startup properties are improved. A fuel cell has a cell stack in which a plurality of unit cells are stacked, and terminal plates disposed on both sides of the cell stack in a cell stack direction thereof. The fuel cell comprises an insulating portion having an insulating material and holding plates which hold the insulating material from both the sides of the insulating material in the cell stack direction, the insulating material is held between the holding plates, and the insulating material has a thermal conductivity of 0.1 W/mK or less and a porosity of 70% or more.

Abstract: A first communication apparatus includes a first central processing core; and a first memory. The first communication apparatus executes load distribution based on a first load amount of the first communication apparatus and a second load amount of a second communication apparatus that includes a second central processing core and a second memory. The first communication apparatus executes first load distribution when the first communication apparatus and the second communication apparatus perform wireless communication. The first communication apparatus executes second load distribution when the first communication apparatus and the second communication apparatus perform wired communication.

Abstract: The method for producing the porous sheet of the present invention includes the steps of (I) preparing a plurality of sheet materials that contain polytetrafluoroethylene and carbon particles and (II) stacking the plurality of sheet materials over one another and rolling the stacked sheet materials. In the method for producing the porous sheet of the present invention, step (I) and step (II) may be repeated alternately. Further, as the sheet materials to be used in the production method of the present invention, a base sheet obtained by forming a mixture containing polytetrafluoroethylene and carbon particles into sheet form also can be used, or a laminated sheet obtained by stacking a plurality of base sheets over one another and rolling them also can be used, for example.

Abstract: A memory stores data generated by a processor and a transferring unit burst transfers the data from the memory unit to a processing unit. Based on an access capability of the processor when accessing the memory, a prescribed value for a burst width and information concerning the time that the processing unit consumes to process the data are set in advance at the data transferring apparatus. When the transferring unit performs data transfer, the time allowed for data transfer is calculated based on the information concerning the time that the processing unit consumes to process the data, and the burst width is determined as a value greater than or equal to the prescribed value for the burst width and is as close as possible to the prescribed value for the burst width within a range in which data transfer can be finished within the allowed time.

Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

Abstract: A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.

Abstract: A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.

Abstract: A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among the ports. A CPU acquires from a parallel degree information table, the number of CPUs to which software that is to be executed by the multi-core processor system, is to be assigned. After this acquisition, the CPU determines the CPUs to which the software to be executed is to be assigned and sets for each CPU, physical address spaces corresponding to logical address spaces defined by the software to be executed. After this setting, the CPU notifies an address converter of the addresses and notifies the software to be executed of the start of execution.

Abstract: A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request.

Abstract: A data processor includes: a plurality of controllers that process data; a program memory that stores a standby instruction and a data processing instruction at a plurality of addresses respectively; and a queue that stores different execution start addresses for the plurality of controllers, wherein after the plurality of controllers sequentially access the queue, the plurality of controllers acquire the different execution start addresses from the queue in an order of the sequential access, start execution of instructions from the acquired different execution start addresses in the program memory, and execute the data processing instruction and execute the standby instruction the number of times different for each of the controllers.

Abstract: A data processing apparatus includes a storage unit configured to store plural data processing programs and a corresponding error processing program for when an error occurs with a first data processing program; and a processor configured to record to memory before executing the first data processing program, information of the error processing program that corresponds to the first data processing program; update and record in the memory after the first data processing program ends, information of a second data processing program scheduled to be executed next; and switch to any one among the first data processing program that corresponds to information recorded in the memory and the error processing program, when program processing is started next.

Abstract: A coprocessor stores to local memory, a driver execution start time, for each execution start of drivers. If a CPU call process is executed during the execution of driver A, the coprocessor calculates the difference of the execution start time and the current time, for drivers B and C. Taking driver C as an example, the coprocessor adds to the difference calculated for the driver C, a processing time required for the CPU call process of driver A and a processing time required for a normal process of driver B. The coprocessor determines whether respective addition results for driver C comply with respective time constraints. If it is determined that an addition result for the driver C cannot comply with the time constraint, and the coprocessor sends an execution request for driver C to another coprocessor.

Abstract: A multi-core system includes processor cores having caches; an external input/output bus connected to the processor cores; memory accessed by the processor cores via the external input/output bus; profile information indicating the volume of a write access to the memory by tasks concurrently allocated to the processor cores and whether a cache miss will occur in a read access to the caches; and an operating system that controls clock frequency of the external input/output bus to be a first frequency, based on the volume of the write access to the memory by the tasks and the bus width of the external input/output bus when a cache miss in read access is judged to not occur in executing the tasks and that controls the clock frequency of the external input/output bus to be a second frequency higher than the first frequency when a cache miss in read access is judged.

Abstract: A detecting apparatus includes processors configured to access sensors; select from among the sensors, a sensor that has not been selected by any processor, acquire data from the selected sensor, and release selection of the sensor when data acquisition has been completed; execute processing for the sensor, based on the acquired data; set the sensor to an execution state during execution of the processing for the sensor, and set the sensor to an execution completed state when the execution of the processing for the sensor has ended; copy from a processor that has set the sensor to the execution state, the data acquired from the sensor by the processor, upon determining the sensor to be in the execution state, without executing the data acquisition; and execute the processing for the sensor, based on the copied data.