Abstract: A method includes forming, by a laser beam supplied by a laser cutting system, a laser-cut line in each of a plurality of glass samples. Each different laser-cut line in each different glass sample of the plurality of glass samples is formed when the laser cutting system is at a different process setting. The method also includes subjecting each of the plurality of glass samples with the laser-cut lines to a break test, and obtaining a plurality of break strength values. Each different break strength value of the plurality of break strength values is indicative of a laser-cut line quality of the respective glass sample of the plurality of glass samples.

Abstract: A method includes forming, by a laser beam supplied by a laser cutting system, a laser-cut line in each of a plurality of glass samples. Each different laser-cut line in each different glass sample of the plurality of glass samples is formed when the laser cutting system is at a different process setting. The method also includes subjecting each of the plurality of glass samples with the laser-cut lines to a break test, and obtaining a plurality of break strength values. Each different break strength value of the plurality of break strength values is indicative of a laser-cut line quality of the respective glass sample of the plurality of glass samples.

Abstract: A semiconductor device includes a common resource commonly used by plural processes executed on a processor, a semaphore controlling the possessory right of the common resource, and a semaphore management unit performing a process of acquiring the possessory right of the common resource to the semaphore in response to a request of a process performed on the processor. When a request to acquire the possessory right of the common resource is received from a first process in the plural processes and the possessory right cannot be obtained, the semaphore management unit switches the process executed on the processor to a second process, repeatedly performs a process of acquiring the possessory right requested by the first process to the semaphore and, when the possessory right requested by the first process is obtained, switches the process on the processor from the second process to the first process.

Abstract: According to one embodiment, a data processing apparatus includes an access controller configured to control access by a CPU to a processor. The access controller selects permission configuration information and an identifier table to be used for the access control using processor selection information output from the CPU, determines as intermediate identifier MID that corresponds to an access request identifier SPID output from the CPU using the selected identifier table, and determines accessibility of the CPU to the processor using the selected permission configuration information and the determined intermediate identifier MID.

Abstract: A data processor includes an access target with the address assigned to a memory space, an access subject that gains access to the access target while specifying address, identifier, and access type, and a memory protection resource including an associative memory to perform an access control. The memory protection resource includes a plurality of entries, each including a region setting unit, an identifier determination information unit, and an attribute setting unit. When the address specified by the access subject at the access is included in the region set in the region setting unit in the entry, the identifier agrees with at least one of the identifiers specified according to the identifier determination information, and the specified access type agrees with the access type set in the attribute setting unit, the memory protection resource permits the access.

Abstract: A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that manages in what order a plurality of hardware threads are processed with a pre-established schedule, and an interrupt controller that receives an input interrupt request signal and assigns the interrupt request to an associated hardware thread, wherein the interrupt controller comprises a register in which information is stored for each channel of an interrupt request signal, and the information includes information regarding to which one or more than one of the plurality of hardware threads the interrupt request signal is associated.

Abstract: A multi-thread processor includes a plurality of hardware threads that generates a plurality of mutually independent instruction streams, respectively and a scheduler that schedules the plurality of hardware threads.

Abstract: A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

Abstract: A semiconductor device includes a common resource commonly used by plural processes executed on a processor, a semaphore controlling the possessory right of the common resource, and a semaphore management unit performing a process of acquiring the possessory right of the common resource to the semaphore in response to a request of a process performed on the processor. When a request to acquire the possessory right of the common resource is received from a first process in the plural processes and the possessory right cannot be obtained, the semaphore management unit switches the process executed on the processor to a second process, repeatedly performs a process of acquiring the possessory right requested by the first process to the semaphore and, when the possessory right requested by the first process is obtained, switches the process on the processor from the second process to the first process.

Abstract: A data processor includes an access target with the address assigned to a memory space, an access subject that gains access to the access target while specifying address, identifier, and access type, and a memory protection resource including an associative memory to perform an access control. The memory protection resource includes a plurality of entries, each including a region setting unit, an identifier determination information unit, and an attribute setting unit. When the address specified by the access subject at the access is included in the region set in the region setting unit in the entry, the identifier agrees with at least one of the identifiers specified according to the identifier determination information, and the specified access type agrees with the access type set in the attribute setting unit, the memory protection resource permits the access.

Abstract: Apparatus and method for magnetic recording media. A rotatable magnetic recording disc has an outermost annular sidewall that extends at nominally 97 millimeters, mm for a 3-½ inch form factor data storage device or at nominally 67 mm for a 2-½ inch form factor data storage device. The rotatable magnetic recording disc further has a disc shaped substrate of metal or glass, and a magnetic recording layer supported by the disc shaped substrate and configured to magnetically record data along concentric tracks.

Abstract: A data processor includes an access target with the address assigned to a memory space, an access subject that gains access to the access target while specifying address, identifier, and access type, and a memory protection resource including an associative memory to perform an access control. The memory protection resource includes a plurality of entries, each including a region setting unit, an identifier determination information unit, and an attribute setting unit. When the address specified by the access subject at the access is included in the region set in the region setting unit in the entry, the identifier agrees with at least one of the identifiers specified according to the identifier determination information, and the specified access type agrees with the access type set in the attribute setting unit, the memory protection resource permits the access.

Abstract: According to one embodiment, a data processing apparatus includes an access controller configured to control access by a CPU to a processor. The access controller selects permission configuration information and an identifier table to be used for the access control using processor selection information output from the CPU, determines as intermediate identifier MID that corresponds to an access request identifier SPID output from the CPU using the selected identifier table, and determines accessibility of the CPU to the processor using the selected permission configuration information and the determined intermediate identifier MID.

Abstract: A multi-thread processor includes a plurality of hardware threads that generates a plurality of mutually independent instruction streams, respectively and a scheduler that schedules the plurality of hardware threads.

Abstract: Apparatus and method for magnetic recording media. A rotatable magnetic recording disc has an outermost annular sidewall that extends at nominally 97 millimeters, mm for a 3½ inch form factor data storage device or at nominally 67 mm for a 2½ inch form factor data storage device. The rotatable magnetic recording disc further has a disc shaped substrate of metal or glass, and a magnetic recording layer supported by the disc shaped substrate and configured to magnetically record data along concentric tracks.

Abstract: The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. A thread waste counter is provided for each hardware thread in the first group and counts up each time a nondispatchable state occurs when the hardware thread is specified by the thread scheduling. When the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.

Abstract: An enlarged substrate configuration for magnetic recording media. In some embodiments, an apparatus comprises a disc shaped member of metal or glass configured as a substrate for a magnetic data recording disc for a 2½ inch form factor data storage device or a 3½ inch form factor data storage device. The disc shaped member has a top planar surface, an opposing bottom planar surface, an outermost annular sidewall that extends between the top planar surface and the bottom planar surface at an outermost diameter of nominally 67 or 97 millimeters, respectively, and an inner annular sidewall that extends between the top planar surface and the bottom planar surface to define a central aperture.

Abstract: An enlarged substrate configuration for magnetic recording media. In some embodiments, an apparatus comprises a disc shaped member of metal or glass configured as a substrate for a magnetic data recording disc for a 2½ inch form factor data storage device or a 3½ inch form factor data storage device. The disc shaped member has a top planar surface, an opposing bottom planar surface, an outermost annular sidewall that extends between the top planar surface and the bottom planar surface at an outermost diameter of nominally 67 or 97 millimeters, respectively, and an inner annular sidewall that extends between the top planar surface and the bottom planar surface to define a central aperture.

Abstract: A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.

Abstract: A data storage device having a housing member for a selected one of a 3½ inch form factor hard disc drive (HDD) or a 2½ inch form factor HDD. A spindle motor coupled to the housing member supports a rotatable data recording disc with a plurality of data tracks and an outermost perimeter. The outermost perimeter has an average overall radius of 48.5 millimeters, mm responsive to the housing member being for a 3½ inch form factor HDD or an average overall radius of 33.5 mm responsive to the housing member being for a 2½ inch form factor HDD. The rotatable data recording disc further has an outermost data track at an average selected radius such that the difference between the average overall radius of the outermost perimeter and the average selected radius is more than 1 mm.