Patents by Inventor Koji Adachi
Koji Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9799364Abstract: An enlarged substrate configuration for magnetic recording media. In some embodiments, an apparatus comprises a disc shaped member of metal or glass configured as a substrate for a magnetic data recording disc for a 2½ inch form factor data storage device or a 3½ inch form factor data storage device. The disc shaped member has a top planar surface, an opposing bottom planar surface, an outermost annular sidewall that extends between the top planar surface and the bottom planar surface at an outermost diameter of nominally 67 or 97 millimeters, respectively, and an inner annular sidewall that extends between the top planar surface and the bottom planar surface to define a central aperture.Type: GrantFiled: May 15, 2017Date of Patent: October 24, 2017Assignee: Seagate Technology LLCInventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, James Hennessy, David Perez
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Publication number: 20170249967Abstract: An enlarged substrate configuration for magnetic recording media. In some embodiments, an apparatus comprises a disc shaped member of metal or glass configured as a substrate for a magnetic data recording disc for a 2½ inch form factor data storage device or a 3½ inch form factor data storage device. The disc shaped member has a top planar surface, an opposing bottom planar surface, an outermost annular sidewall that extends between the top planar surface and the bottom planar surface at an outermost diameter of nominally 67 or 97 millimeters, respectively, and an inner annular sidewall that extends between the top planar surface and the bottom planar surface to define a central aperture.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Inventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, James Hennessy, David Perez
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Publication number: 20170177431Abstract: A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.Type: ApplicationFiled: March 6, 2017Publication date: June 22, 2017Inventors: Hirotaka Motai, Yasuhiro Tawara, Koji Adachi, Hitoshi Suzuki
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Patent number: 9653112Abstract: A data storage device having a housing member for a selected one of a 3½ inch form factor hard disc drive (HDD) or a 2½ inch form factor HDD. A spindle motor coupled to the housing member supports a rotatable data recording disc with a plurality of data tracks and an outermost perimeter. The outermost perimeter has an average overall radius of 48.5 millimeters, mm responsive to the housing member being for a 3½ inch form factor HDD or an average overall radius of 33.5 mm responsive to the housing member being for a 2½ inch form factor HDD. The rotatable data recording disc further has an outermost data track at an average selected radius such that the difference between the average overall radius of the outermost perimeter and the average selected radius is more than 1 mm.Type: GrantFiled: November 28, 2016Date of Patent: May 16, 2017Assignee: Seagate Technology LLCInventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, James Hennessy, David Perez
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Publication number: 20170109202Abstract: The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. A thread waste counter is provided for each hardware thread in the first group and counts up each time a nondispatchable state occurs when the hardware thread is specified by the thread scheduling. When the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.Type: ApplicationFiled: December 29, 2016Publication date: April 20, 2017Inventors: Junichi SATO, Koji ADACHI, Yousuke NAKAMURA
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Patent number: 9612909Abstract: A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred.Type: GrantFiled: October 20, 2015Date of Patent: April 4, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hirotaka Motai, Yasuhiro Tawara, Koji Adachi, Hitoshi Suzuki
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Publication number: 20170091125Abstract: A data processor includes an access target with the address assigned to a memory space, an access subject that gains access to the access target while specifying address, identifier, and access type, and a memory protection resource including an associative memory to perform an access control. The memory protection resource includes a plurality of entries, each including a region setting unit, an identifier determination information unit, and an attribute setting unit. When the address specified by the access subject at the access is included in the region set in the region setting unit in the entry, the identifier agrees with at least one of the identifiers specified according to the identifier determination information, and the specified access type agrees with the access type set in the attribute setting unit, the memory protection resource permits the access.Type: ApplicationFiled: August 20, 2016Publication date: March 30, 2017Inventors: Koji ADACHI, Yoichi YUYAMA
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Publication number: 20170076750Abstract: A data storage device having a housing member for a selected one of a 3½ inch form factor hard disc drive (HDD) or a 2½ inch form factor HDD. A spindle motor coupled to the housing member supports a rotatable data recording disc with a plurality of data tracks and an outermost perimeter. The outermost perimeter has an average overall radius of 48.5 millimeters, mm responsive to the housing member being for a 3½ inch form factor HDD or an average overall radius of 33.5 mm responsive to the housing member being for a 2½ inch form factor HDD. The rotatable data recording disc further has an outermost data track at an average selected radius such that the difference between the average overall radius of the outermost perimeter and the average selected radius is more than 1 mm.Type: ApplicationFiled: November 28, 2016Publication date: March 16, 2017Inventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, James Hennessy, David Perez
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Publication number: 20170046155Abstract: A multi-thread processor including a plurality of hardware threads each of which is configured to generate an independent instruction flow, a thread scheduler configured to output a thread selection signal according to a schedule, the thread selection signal being a signal for selecting a hardware thread to be used in a next execution cycle from among the plurality of hardware threads, a first selector configured to select and output an instruction generated by the hardware thread selected according to the thread selection signal, and an arithmetic circuit configured to execute the instruction output from the first selector. The thread scheduler selects at least one hardware thread selected in a fixed manner from among the plurality of hardware threads in a predetermined first execution period and selects an arbitrary hardware thread in a second execution period other than the first execution period.Type: ApplicationFiled: November 1, 2016Publication date: February 16, 2017Inventors: Koji Adachi, Kazunori Miyamoto
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Patent number: 9569261Abstract: The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. Moreover, when the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.Type: GrantFiled: October 15, 2013Date of Patent: February 14, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Junichi Sato, Koji Adachi, Yousuke Nakamura
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Patent number: 9529597Abstract: A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that continuously outputs a thread selection signal uniformly in a first period of a cycle of the first schedule pattern in accordance with a first schedule pattern or continuously outputs the thread selection signal uniformly in a second period of a cycle of the second schedule pattern in accordance with a second schedule pattern, the thread selection signal designating a hardware thread to be executed in a next execution cycle from among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread from among the plurality of hardware threads, and an execution pipeline that executes an instruction output from the first selector.Type: GrantFiled: August 12, 2013Date of Patent: December 27, 2016Assignee: Renesas Electronics CorporationInventors: Koji Adachi, Toshiyuki Matsunaga
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Patent number: 9508374Abstract: A hard disc drive (HDD) with an enlarged magnetic recording disc. In some embodiments, a base deck and top cover are arranged to provide an HDD housing with a 2½ inch form factor or a 3½ inch form factor. A magnetic recording disc is supported for rotation within the housing. A data transducer is controllably advanced across a recording surface of the magnetic recording disc to write data to the recording surface, and a printed circuit board assembly (PCBA) affixed to an external surface of the base deck incorporates control electronics to provide write signals to the data transducer during the writing of data to the recording surface. The disc has an outer diameter of at least 67 millimeters, mm for the 2½ inch form factor housing and has an outer diameter of at least 97 mm for the 3½ inch form factor housing.Type: GrantFiled: June 6, 2016Date of Patent: November 29, 2016Assignee: Seagate Technology LLCInventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, James Hennessy, David Perez
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Patent number: 9501320Abstract: A multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, and a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread. The thread scheduler specifies execution of at least one hardware thread pre-selected among the plurality of hardware threads in a predetermined first execution period, and specifies execution of a variably selected hardware thread in a second execution period other than the first execution period. A time ratio between the predetermined first execution period and the second execution period is set according to processing requests.Type: GrantFiled: November 27, 2013Date of Patent: November 22, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koji Adachi, Kazunori Miyamoto
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Patent number: 9495624Abstract: Provided is an estimation apparatus including a storage unit that stores an estimation model for estimating transport failure information pertaining to a transport failure based on information pertaining to a transit time in which each of plural papers with different characteristics passes through a certain transport section in a transport path and information pertaining to a utilization of each of the plural papers for each of plural image processing apparatuses, an acquisition unit that acquires the characteristics of the paper, information pertaining to the transit time of the paper, and information pertaining to the utilization of the paper for the image processing apparatus that is the estimation target, and an estimation unit that estimates the transport failure information using the estimation model based on the acquisition results of the acquisition unit.Type: GrantFiled: September 1, 2015Date of Patent: November 15, 2016Assignee: FUJI XEROX CO., LTD.Inventor: Koji Adachi
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Patent number: 9465610Abstract: A semiconductor device includes an execution unit that executes an arithmetic instruction, and a scheduler including multiple first setting registers each defining a correspondence relationship between hardware threads and partitions, and which generates a thread select signal on the basis of a partition schedule and a thread schedule. The scheduler outputs a thread select signal designating a specific hardware thread, without depending on the thread schedule as the partition indicated by a first occupation control signal, according to a first occupation control signal output when the execution unit executes a first occupation start instruction.Type: GrantFiled: April 9, 2013Date of Patent: October 11, 2016Assignee: Renesas Electronics CorporationInventors: Hitoshi Suzuki, Koji Adachi
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Patent number: 9462149Abstract: Provided is a parameter setting system, including a storage unit that memorizes a history of parameter values in an image forming apparatus in association with a type of paper, an acquiring unit that acquires a trend of parameter values in plural image forming apparatuses of the same type with the image forming apparatus with respect to each type of plural other paper sheets in which the number of types of switched paper and the number of histories are greater than or equal to a threshold value, and a calculating unit that calculates a parameter value to be set with respect to the type of switched paper based on the trend of parameter values acquired with respect to the type of switched paper and each type of the plural other paper sheets, and the history corresponding to each type of the plural other paper sheets.Type: GrantFiled: August 25, 2014Date of Patent: October 4, 2016Assignee: FUJI XEROX CO., LTD.Inventor: Koji Adachi
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Publication number: 20160284373Abstract: A hard disc drive (HDD) with an enlarged magnetic recording disc. In some embodiments, a base deck and top cover are arranged to provide an HDD housing with a 2½ inch form factor or a 3½ inch form factor. A magnetic recording disc is supported for rotation within the housing. A data transducer is controllably advanced across a recording surface of the magnetic recording disc to write data to the recording surface, and a printed circuit board assembly (PCBA) affixed to an external surface of the base deck incorporates control electronics to provide write signals to the data transducer during the writing of data to the recording surface. The disc has an outer diameter of at least 67 millimeters, mm for the 2½ inch form factor housing and has an outer diameter of at least 97 mm for the 3½ inch form factor housing.Type: ApplicationFiled: June 6, 2016Publication date: September 29, 2016Inventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, James Hennessy, David Perez
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Publication number: 20160232435Abstract: Provided is an estimation apparatus including a storage unit that stores an estimation model for estimating transport failure information pertaining to a transport failure based on information pertaining to a transit time in which each of plural papers with different characteristics passes through a certain transport section in a transport path and information pertaining to a utilization of each of the plural papers for each of plural image processing apparatuses, an acquisition unit that acquires the characteristics of the paper, information pertaining to the transit time of the paper, and information pertaining to the utilization of the paper for the image processing apparatus that is the estimation target, and an estimation unit that estimates the transport failure information using the estimation model based on the acquisition results of the acquisition unit.Type: ApplicationFiled: September 1, 2015Publication date: August 11, 2016Inventor: Koji ADACHI
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Patent number: 9361925Abstract: An enlarged substrate for a magnetic recording medium used in a data storage device such as a hard disc drive (HDD). In some embodiments, a data storage device has a housing member for a 3½ inch form factor storage device or a 2½ inch form factor storage device. A rotatable data recording disc is supported by the housing member. The disc has a plurality of tracks formed thereon. At least one track of the plurality of tracks has an average radius of greater than 47.5 mm for the 3½ inch form factor storage device or greater than 32.5 mm for the 2½ inch form factor storage device. A data read/write transducer is configured to be controllably advanced across a recording surface of the data recording disc and to record data to the plurality of tracks.Type: GrantFiled: January 4, 2016Date of Patent: June 7, 2016Assignee: Seagate Technology LLCInventors: Koji Adachi, Ian J. Beresford, Thomas Y Chang, Kuo Hsing Hwang, James Hennessy, David Perez
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Publication number: 20160118072Abstract: An enlarged substrate for a magnetic recording medium used in a data storage device such as a hard disc drive (HDD). In some embodiments, a data storage device has a housing member for a 3½ inch form factor storage device or a 2½ inch form factor storage device. A rotatable data recording disc is supported by the housing member. The disc has a plurality of tracks formed thereon. At least one track of the plurality of tracks has an average radius of greater than 47.5 mm for the 3½ inch form factor storage device or greater than 32.5 mm for the 2½ inch form factor storage device. A data read/write transducer is configured to be controllably advanced across a recording surface of the data recording disc and to record data to the plurality of tracks.Type: ApplicationFiled: January 4, 2016Publication date: April 28, 2016Inventors: Koji Adachi, Ian J. Beresford, Thomas Y. Chang, Kuo Hsing Hwang, James Hennessy, David Perez