Abstract: A defect density calculation method according to one embodiment of the present disclosure is a method of calculating a temporal change of the defect density distribution in a semiconductor layer. The method includes calculating the temporal change of the defect density distribution on the basis of an arithmetic function using at least the activation energy of a detect included in the semiconductor layer, the processing temperature of the semiconductor layer, and the processing time of the semiconductor layer as arguments.

Abstract: At least a laminate of a gate insulating film 6 and a gate electrode 7 and an active region 13 are formed on a silicon substrate 1, and an underlying interlayer insulating film 10 is further formed. Then, a conductor 11a connected to the gate electrode 7, and a conductor 11b that is a dummy conductor and is connected to the active region 13 are formed simultaneously on the underlying interlayer insulating film 10. Thereafter, an interlayer insulating film 12 is formed on the underlying interlayer insulating film 10 by a plasma process. At this time, charging current from a plasma 14 is emitted through the conductor 11b, which is a dummy conductor.

Abstract: At least a laminate of a gate insulating film 6 and a gate electrode 7 and an active region 13 are formed on a silicon substrate 1, and an underlying interlayer insulating film 10 is further formed. Then, a conductor 11a connected to the gate electrode 7, and a conductor 11b that is a dummy conductor and is connected to the active region 13 are formed simultaneously on the underlying interlayer insulating film 10. Thereafter, an interlayer insulating film 12 is formed on the underlying interlayer insulating film 10 by a plasma process. At this time, charging current from a plasma 14 is emitted through the conductor 11b, which is a dummy conductor.

Abstract: At least a laminate of a gate insulating film 6 and a gate electrode 7 and an active region 13 are formed on a silicon substrate 1, and an underlying interlayer insulating film 10 is further formed. Then, a conductor 11a connected to the gate electrode 7, and a conductor 11b that is a dummy conductor and is connected to the active region 13 are formed simultaneously on the underlying interlayer insulating film 10. Thereafter, an interlayer insulating film 12 is formed on the underlying interlayer insulating film 10 by a plasma process. At this time, charging current from a plasma 14 is emitted through the conductor 11b, which is a dummy conductor.

Abstract: A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contact 31 and a bit line 32 extending on an inter-level dielectric 30. In a memory cell transistor, a source diffusion layer 18 is covered with two dielectric sidewalls 25a and 25b in the memory cell transistor so that no silicide layer is formed on the source diffusion layer 18. A plate contact 31 is provided to pass through the inter-level dielectric 30 and connect a shield line 33 to a plate electrode 16b. The shield line 33 is arranged in the same interconnect layer as the bit line 32.

Abstract: A top surface of a wafer is provided with an n-type source region, an n-type drain region, and an n-type semiconductor region. Dry etching using a plasma is performed with respect to an interlayer insulating film deposited on the wafer to form openings reaching the respective regions, followed by light etching for removing a damaged layer. In this case, exciting light is supplied intermittently to the n-type semiconductor region. The progression of the removal of the damaged layer and the stage of development of a newly damaged layer are sensed by monitoring the change rate of the intensity of reflected probe light in the presence and absence of the exciting light, resulting in the formation of a semiconductor device having low and equal contact resistance. In-line control using optical evaluation enables the implementation of semiconductor devices with excellent and consistent properties.

Abstract: At least a laminate of a gate insulating film 6 and a gate electrode 7 and an active region 13 are formed on a silicon substrate 1, and an underlying interlayer insulating film 10 is further formed. Then, a conductor 11a connected to the gate electrode 7, and a conductor 11b that is a dummy conductor and is connected to the active region 13 are formed simultaneously on the underlying interlayer insulating film 10. Thereafter, an interlayer insulating film 12 is formed on the underlying interlayer insulating film 10 by a plasma process. At this time, charging current from a plasma 14 is emitted through the conductor 11b, which is a dummy conductor.

Abstract: A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contact 31 and a bit line 32 extending on an inter-level dielectric 30. In a memory cell transistor, a source diffusion layer 18 is covered with two dielectric sidewalls 25a and 25b in the memory cell transistor so that no silicide layer is formed on the source diffusion layer 18. A plate contact 31 is provided to pass through the inter-level dielectric 30 and connect a shield line 33 to a plate electrode 16b. The shield line 33 is arranged in the same interconnect layer as the bit line 32.

Abstract: There is provided a clustered device for manufacturing a semiconductor device in which a cleaning chamber, a rapid thermal processing chamber, an optical measurement chamber, and the like are arranged around a load-lock room. In an optical measurement system, there are disposed an exciting light source, a measuring light source, a light detector, a control/analyze system, and the like. During the formation of an oxide film, for example, a wafer is cleaned in the cleaning chamber and then the amount of a natural oxide film remaining on the wafer or the like is measured by optical modulation reflectance spectroscopy in the optical measurement chamber. Thereafter, the wafer is oxidized in the rapid thermal processing chamber. As a result, the surface of the wafer is prevented from being oxidized on exposure to an atmosphere and the surface state of the wafer can be monitored in the course of sequential process steps.

Abstract: A high dielectric film is formed by utilizing atom injection into a film through ion implantation or the like, and heat treatment. For example, an SiO2 film 102 which is a thermal oxide film is formed on a silicon substrate 101, and then Zr ions (Zr+) are injected from a plasma 105 into the SiO2 film 102. Thereafter, by annealing the SiO2 film 102 and a Zr injected layer 103, injected Zr is diffused in the Zr injected layer 103 and then the SiO2 film 102 and the Zr injected layer 103 are as a whole changed into a high dielectric film 106 of a high dielectric constant formed of Zr—Si—O (silicate). By using the high dielectric film 106 as an insulating film for an MISFET, an MISFET having excellent gate leakage properties can be achieved.

Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).

Abstract: A top surface of a wafer is provided with an n-type source region, an n-type drain region, and an n-type semiconductor region. Dry etching using a plasma is performed with respect to an interlayer insulating film deposited on the wafer to form openings reaching the respective regions, followed by light etching for removing a damaged layer. In this case, exciting light is supplied intermittently to the n-type semiconductor region. The progression of the removal of the damaged layer and the stage of development of a newly damaged layer are sensed by monitoring the change rate of the intensity of reflected probe light in the presence and absence of the exciting light, resulting in the formation of a semiconductor device having low and equal contact resistance. In-line control using optical evaluation enables the implementation of semiconductor devices with excellent and consistent properties.

Abstract: There is provided a method for evaluating an insulating film entirely provided on a conductor layer for the characteristics or dimensions thereof. A measuring member having conductor bumps arranged thereon to be connected to wires is disposed above the insulating film on the conductor layer. Then, the conductor bumps are pressed against the insulating film with a given pressing force. By applying a voltage (electric stress) between the conductor bumps and the conductor layer, the characteristics including I-V characteristic, gate leakage current, and TDDB or the dimensions including thickness are evaluated.

Abstract: There is provided a clustered device for manufacturing a semiconductor device in which a cleaning chamber, a rapid thermal processing chamber, an optical measurement chamber, and the like are arranged around a load-lock room. In an optical measurement system, there are disposed an exciting light source, a measuring light source, a light detector, a control/analyze system, and the like. During the formation of an oxide film, for example, a wafer is cleaned in the cleaning chamber and then the amount of a natural oxide film remaining on the wafer or the like is measured by optical modulation reflectance spectroscopy in the optical measurement chamber. As a result, the surface state of the wafer can be monitored in the course of sequential process steps. By measuring the thickness of a film on a semiconductor region by optical evaluation in the clustered manufacturing device, the manufacturing process using the clustered device can be controlled.

Abstract: A top surface of a wafer is provided with an n-type source region, an n-type drain region, and an n-type semiconductor region. Dry etching using a plasma is performed with respect to an interlayer insulating film deposited on the wafer to form openings reaching the respective regions, followed by light etching for removing a damaged layer. In this case, exciting light is supplied intermittently to the n-type semiconductor region. The progression of the removal of the damaged layer and the stage of development of a newly damaged layer are sensed by monitoring the change rate of the intensity of reflected probe light in the presence and absence of the exciting light, resulting in the formation of a semiconductor device having low and equal contact resistance. In-line control using optical evaluation enables the implementation of semiconductor devices with excellent and consistent properties.

Abstract: There is provided a method for evaluating an insulating film entirely provided on a conductor layer for the characteristics or dimensions thereof. A measuring member having conductor bumps arranged thereon to be connected to wires is disposed above the insulating film on the conductor layer. Then, the conductor bumps are pressed against the insulating film with a given pressing force. By applying a voltage (electric stress) between the conductor bumps and the conductor layer, the characteristics including I-V characteristic, gate leakage current, and TDDB or the dimensions including thickness are evaluated.

Abstract: There is provided a method for evaluating an insulating film entirely provided on a conductor layer for the characteristics or dimensions thereof. A measuring member having conductor bumps arranged thereon to be connected to wires is disposed above the insulating film on the conductor layer. Then, the conductor bumps are pressed against the insulating film with a given pressing force. By applying a voltage (electric stress) between the conductor bumps and the conductor layer, the characteristics including I-V characteristic, gate leakage current, and TDDB or the dimensions including thickness are evaluated.

Abstract: A top surface of a wafer is provided with an n-type source region, an n-type drain region, and an n-type semiconductor region. Dry etching using a plasma is performed with respect to an interlayer insulating film deposited on the wafer to form openings reaching the respective regions, followed by light etching for removing a damaged layer. In this case, exciting light is supplied intermittently to the n-type semiconductor region. The progression of the removal of the damaged layer and the stage of development of a newly damaged layer are sensed by monitoring the change rate of the intensity of reflected probe light in the presence and absence of the exciting light, resulting in the formation of a semiconductor device having low and equal contact resistance. In-line control using optical evaluation enables the implementation of semiconductor devices with excellent and consistent properties.

Abstract: A high dielectric film is formed by utilizing atom injection into a film through ion implantation or the like, and heat treatment. For example, an SiO2 film 102 which is a thermal oxide film is formed on a silicon substrate 101, and then Zr ions (Zr+) are injected from a plasma 105 into the SiO2 film 102. Thereafter, by annealing the SiO2 film 102 and a Zr injected layer 103, injected Zr is diffused in the Zr injected layer 103 and then the SiO2 film 102 and the Zr injected layer 103 are as a whole changed into a high dielectric film 106 of a high dielectric constant formed of Zr—Si—O (silicate). By using the high dielectric film 106 as an insulating film for an MISFET, an MISFET having excellent gate leakage properties can be achieved.

Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).