Patents by Inventor Koji Eriguchi
Koji Eriguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6489629Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).Type: GrantFiled: February 7, 2000Date of Patent: December 3, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Eriguchi, Masafumi Kubota, Masaaki Niwa, Noboru Nomura
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Patent number: 6469535Abstract: A particular portion of a damaged layer within a semiconductor substrate, which is likely to affect the performance of resulting semiconductor devices, is distinguished from the other negligible portions thereof and the depth of that non-negligible portion is detected. An Si substrate is placed on a stage, and a mercury electrode, which forms a Schottky barrier with the Si substrate, is brought into contact with the surface of the Si substrate. When a constant current is supplied from a constant current source between the mercury electrode and the Si substrate, charges are trapped at the trap centers in the damaged layer within the Si substrate. As a result, a potential on the conduction band rises near the surface of the Si substrate. And if the voltage between the electrode and the substrate is increased along with the potential rise, a constant current flows.Type: GrantFiled: June 8, 1999Date of Patent: October 22, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kyoko Egashira, Koji Eriguchi
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Publication number: 20020135785Abstract: There is provided a clustered device for manufacturing a semiconductor device in which a cleaning chamber, a rapid thermal processing chamber, an optical measurement chamber, and the like are arranged around a load-lock room. In an optical measurement system, there are disposed an exciting light source, a measuring light source, a light detector, a control/analyze system, and the like. During the formation of an oxide film, for example, a wafer is cleaned in the cleaning chamber and then the amount of a natural oxide film remaining on the wafer or the like is measured by optical modulation reflectance spectroscopy in the optical measurement chamber. Thereafter, the wafer is oxidized in the rapid thermal processing chamber. As a result, the surface of the wafer is prevented from being oxidized on exposure to an atmosphere and the surface state of the wafer can be monitored in the course of sequential process steps.Type: ApplicationFiled: May 20, 2002Publication date: September 26, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Koji Eriguchi
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Publication number: 20020129476Abstract: There is provided a clustered device for manufacturing a semiconductor device in which a cleaning chamber, a rapid thermal processing chamber, an optical measurement chamber, and the like are arranged around a load-lock room. In an optical measurement system, there are disposed an exciting light source, a measuring light source, a light detector, a control/analyze system, and the like. During the formation of an oxide film, for example, a wafer is cleaned in the cleaning chamber and then the amount of a natural oxide film remaining on the wafer or the like is measured by optical modulation reflectance spectroscopy in the optical measurement chamber. Thereafter, the wafer is oxidized in the rapid thermal processing chamber. As a result, the surface of the wafer is prevented from being oxidized on exposure to an atmosphere and the surface state of the wafer can be monitored in the course of sequential process steps.Type: ApplicationFiled: May 20, 2002Publication date: September 19, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Koji Eriguchi
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Patent number: 6395563Abstract: There is provided a clustered device for manufacturing a semiconductor device in which a cleaning chamber, a rapid thermal processing chamber, an optical measurement chamber, and the like are arranged around a load-lock room. In an optical measurement system, there are disposed an exciting light source, a measuring light source, a light detector, a control/analyze system, and the like. During the formation of an oxide film, for example, a wafer is cleaned in the cleaning chamber and then the amount of a natural oxide film remaining on the wafer or the like is measured by optical modulation reflectance spectroscopy in the optical measurement chamber. Thereafter, the wafer is oxidized in the rapid thermal processing chamber. As a result, the surface of the wafer is prevented from being oxidized on exposure to an atmosphere and the surface state of the wafer can be monitored in the course of a sequential process steps.Type: GrantFiled: October 27, 1999Date of Patent: May 28, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Koji Eriguchi
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Patent number: 6372082Abstract: A polysilicon layer is formed on a silicon substrate. A resist film, which has a pattern of remaining portions and opening portions, is formed on the polysilicon layer. The silicon substrate is placed in a reaction chamber, an etch gas is introduced into the reaction chamber, and the introduced gas becomes ionized whereupon dry etching is performed to selectively etch away the polysilicon layer to form projections underneath the remaining portions and recesses underneath the opening portions. By controlling the pressure of the etch gas to fall within a range above 5 millitorr and the flow rate of the etch gas to fall within a range above 100 sccm, both the rate that an etch product is discharged above a recess and the rate that an etch product sticks to a projection sidewall are controlled. Such arrangement not only reduces a critical dimension difference (i.e.Type: GrantFiled: March 31, 2000Date of Patent: April 16, 2002Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Koji Eriguchi
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Publication number: 20020024351Abstract: There is provided a method for evaluating an insulating film entirely provided on a conductor layer for the characteristics or dimensions thereof. A measuring member having conductor bumps arranged thereon to be connected to wires is disposed above the insulating film on the conductor layer. Then, the conductor bumps are pressed against the insulating film with a given pressing force. By applying a voltage (electric stress) between the conductor bumps and the conductor layer, the characteristics including I-V characteristic, gate leakage current, and TDDB or the dimensions including thickness are evaluated.Type: ApplicationFiled: March 15, 2001Publication date: February 28, 2002Inventors: Koji Eriguchi, Yukiko Hashimoto, Akio Watakabe
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Patent number: 6177291Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon. each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).Type: GrantFiled: February 8, 2000Date of Patent: January 23, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Eriguchi, Masafumi Kubota, Masaaki Niwa, Noboru Nomura
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Patent number: 6113733Abstract: A top surface of a wafer is provided with an n-type source region, an n-type drain region, and an n-type semiconductor region. Dry etching using a plasma is performed with respect to an interlayer insulating film deposited on the wafer to form openings reaching the respective regions, followed by light etching for removing a damaged layer. In this case, exciting light is supplied intermittently to the n-type semiconductor region. The progression of the removal of the damaged layer and the stage of development of a newly damaged layer are sensed by monitoring the change rate of the intensity of reflected probe light in the presence and absence of the exciting light, resulting in the formation of a semiconductor device having low and equal contact resistance. In-line control using optical evaluation enables the implementation of semiconductor devices with excellent and consistent properties.Type: GrantFiled: November 7, 1997Date of Patent: September 5, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Eriguchi, Takayuki Yamada, Masanori Okuyama
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Patent number: 6087197Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).Type: GrantFiled: January 8, 1999Date of Patent: July 11, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Eriguchi, Masafumi Kubota, Masaaki Niwa, Noboru Nomura
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Patent number: 6069090Abstract: A polysilicon layer is formed on a silicon substrate. A resist film, which has a pattern of remaining portions and opening portions, is formed on the polysilicon layer. The silicon substrate is placed in a reaction chamber, an etch gas is introduced into the reaction chamber, and the introduced gas becomes ionized whereupon dry etching is performed to selectively etch away the polysilicon layer to form projections underneath the remaining portions and recesses underneath the opening portions. By controlling the pressure of the etch gas to fall within a range above 5 millitorr and the flow rate of the etch gas to fall within a range above 100 sccm, both the rate that an etch product is discharged above a recess and the rate that an etch product sticks to a projection sidewall are controlled. Such arrangement not only reduces a critical dimension difference (i.e.Type: GrantFiled: October 31, 1995Date of Patent: May 30, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Koji Eriguchi
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Patent number: 6033928Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).Type: GrantFiled: November 2, 1994Date of Patent: March 7, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Eriguchi, Masafumi Kubota, Masaaki Niwa, Noboru Nomura
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Patent number: 5985032Abstract: In the process of dry etching or the like, the bond between specific atoms contained in a deposit attached on the interior wall of a chamber and composed of an etching by-product is monitored by using an infrared ray. An incoming infrared ray generated from a light source for monitoring is directed to the deposit so that the absorption spectrum of an outgoing infrared ray passing through the deposit is measured by an infrared-ray measuring device. As a result, accurate information on the inside of the chamber can be obtained and a reduction in production yield due to variations in etching characteristics and generated particles can be prevented. Moreover, the availability of an apparatus can be increased by optimizing a maintenance cycle based on a specific variation in the absorption spectrum of the infrared ray. In particular, process administration and process control in such processing using plasma as dry etching and plasma CVD can be improved.Type: GrantFiled: May 14, 1996Date of Patent: November 16, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Koji Eriguchi
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Patent number: 5903031Abstract: In a first region of a semiconductor substrate, there are formed MIS transistors each composed of a gate insulating film, a gate electrode, and source/drain regions. In a second region of the semiconductor substrate, there is formed an impurity diffusion layer serving as a conductive layer. On an interlayer insulating film, there are formed an antenna interconnection connected to the gate electrodes and an interconnection for charge dissipation connected to the conductive layer. During the process of dry etching for forming the interconnections, charges move into the semiconductor substrate via the interconnection for charge dissipation. The deterioration of the gate insulating film caused by the injection of charges into the gate electrode is suppressed and the degradation of characteristics of the MIS transistor including a shift in threshold is also suppressed.Type: GrantFiled: July 3, 1996Date of Patent: May 11, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takayuki Yamada, Takashi Nakabayashi, Masatoshi Arai, Toshiki Yabu, Koji Eriguchi
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Patent number: 5897378Abstract: In the process of dry etching or the like, the bond between specific atoms contained in a deposit attached on the interior wall of a chamber and composed of an etching by-product is monitored by using an infrared ray. An incoming infrared ray generated from a light source for monitoring is directed to the deposit so that the absorption spectrum of an outgoing infrared ray passing through the deposit is measured by an infrared-ray measuring device. As a result, accurate information on the inside of the chamber can be obtained and a reduction in production yield due to variations in etching characteristics and generated particles can be prevented. Moreover, the availability of an apparatus can be increased by optimizing a maintenance cycle based on a specific variation in the absorption spectrum of the infrared ray. In particular, process administration and process control in such processing using plasma as dry etching and plasma CVD can be improved.Type: GrantFiled: October 19, 1998Date of Patent: April 27, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Koji Eriguchi
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Patent number: 5898207Abstract: A semiconductor device with a damage-free insulating layer is fabricated. A method includes the steps of: forming a first insulating layer on a semiconductor substrate, forming a conductive layer on the first insulating layer, patterning the conductive layer to form a gate electrode, forming low-concentration source/drain region by a first ion implantation, removing a portion of the insulating layer positioned under the side end of the gate electrode, forming a second insulating layer over the semiconductor substrate, the second insulating layer is etched to form a sidewall, forming a high-concentration source/drain region by a second ion implantation.Type: GrantFiled: February 13, 1997Date of Patent: April 27, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Michihiko Takase, Koji Eriguchi, Bunji Mizuno, Masatoshi Arai
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Patent number: 5650336Abstract: A plurality of different constant currents are implanted into an element of a semiconductor device such as a gate oxide film and a metal wire, a charge-to-breakdown (or a breakdown time) is measured from a result of current implantation, a relationship between a constant current value and the charge-to-breakdown (or a breakdown time) is determined, and a time-sequence change in the current during application of a constant voltage is presumed. Next, of a time-sequence change characteristic of the current during application of the constant voltage, current values during the respective minute periods are approximated to a constant current value. Consumption ratios of the life time due to the respective current values are calculated based on a relationship between the constant current value and the charge-to-breakdown (or a breakdown time).Type: GrantFiled: September 18, 1995Date of Patent: July 22, 1997Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koji Eriguchi, Yukiharu Uraoka