Patents by Inventor Koji Hamaguchi

Koji Hamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240032786
    Abstract: A controller of an ophthalmic apparatus finely drives and roughly drives a drive unit of an optometry unit. In a case where a tilt operation of tilting the operation stick within a predetermined range is detected by an operation detection unit, the controller finely drives the drive unit by controlling the drive unit in response to the detected tilt operation, and finely changes a position of the optometry unit. In a case where at least one of a tilt operation of tilting the operation stick over a predetermined range and an operation of a rough movement operation unit is detected by the operation detection unit, the controller roughly drives the drive unit by controlling the drive unit in response to the detected operation, and roughly changes the position of the optometry unit.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 1, 2024
    Applicant: NIDEK CO., LTD.
    Inventors: Kenji Aoki, Koji Hamaguchi, Kenji Nakamura, Hiroyuki Umano, Yuuto Yoshimura
  • Publication number: 20240016472
    Abstract: An ultrasonic tonometer for measuring intraocular pressure of a subject eye by using an ultrasonic wave. The ultrasonic tonometer includes an irradiation unit configured to irradiate the subject eye with a focused ultrasonic wave, and a Z-alignment detection unit configured to detect an alignment state in a working distance direction with respect to the subject eye. An appropriate Z-alignment position is set to a position that is farther from the irradiation unit than is a geometric focal position of the irradiation unit. The appropriate Z-alignment position is detected by the Z-alignment detection unit.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 18, 2024
    Applicant: NIDEK CO., LTD.
    Inventors: Tsutomu UEMURA, Kazunari SHIMIZU, Koji HAMAGUCHI
  • Patent number: 11771316
    Abstract: Provided is a method for an ophthalmic examination by an ophthalmic examination system including an ophthalmic examination apparatus and an examiner-side apparatus that is connected to the ophthalmic examination apparatus by a network and is provided with an interface for input/output, the method including: a transmission step of transmitting an error signal from the ophthalmic examination apparatus to the examiner-side apparatus upon occurrence of an error in the ophthalmic examination apparatus; a selection step of, upon the examiner-side apparatus receiving the error signal, notifying an examiner of the occurrence of the error via the interface and also accepting selection input for selecting any of a plurality of predetermined handling methods of the error; a response step of the examiner-side apparatus transmitting a response signal to the ophthalmic examination apparatus on the basis of the selection input; and a notification step of, upon the ophthalmic examination apparatus receiving the response sign
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: October 3, 2023
    Assignee: NIDEK CO., LTD.
    Inventors: Shirohisa Kobayashi, Kazunari Shimizu, Koji Hamaguchi, Miki Tomiyasu, Tsutomu Uemura
  • Publication number: 20210169323
    Abstract: Provided is a method for an ophthalmic examination by an ophthalmic examination system including an ophthalmic examination apparatus and an examiner-side apparatus that is connected to the ophthalmic examination apparatus by a network and is provided with an interface for input/output, the method including: a transmission step of transmitting an error signal from the ophthalmic examination apparatus to the examiner-side apparatus upon occurrence of an error in the ophthalmic examination apparatus; a selection step of, upon the examiner-side apparatus receiving the error signal, notifying an examiner of the occurrence of the error via the interface and also accepting selection input for selecting any of a plurality of predetermined handling methods of the error; a response step of the examiner-side apparatus transmitting a response signal to the ophthalmic examination apparatus on the basis of the selection input; and a notification step of, upon the ophthalmic examination apparatus receiving the response sign
    Type: Application
    Filed: December 1, 2020
    Publication date: June 10, 2021
    Inventors: Shirohisa Kobayashi, Kazunari Shimizu, Koji Hamaguchi, Miki Tomiyasu, Tsutomu Uemura
  • Patent number: 10012206
    Abstract: A runner vane of an axial hydraulic machine according to embodiments described herein includes a center-side vane part provided on a radial center side and defined by a center-side camber line, and a boss-side vane part provided at a side edge on a side of a runner boss and defined by a boss-side camber line. As determined by the flow direction of a turbine, a curvature of an upstream side portion of the boss-side camber line is larger than a curvature of an upstream side portion of the center-side camber line. An upstream end of the boss-side vane part is positioned on a side of a rotation direction of a runner in comparison with an upstream end of the center-side vane part when viewed toward a downstream side along a rotation axis line of the runner.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: July 3, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Pohan Ko, Koji Hamaguchi
  • Publication number: 20160245256
    Abstract: A runner vane of an axial hydraulic machine according to embodiments described herein includes a center-side vane part provided on a radial center side and defined by a center-side camber line, and a boss-side vane part provided at a side edge on a side of a runner boss and defined by a boss-side camber line. As determined by the flow direction of a turbine, a curvature of an upstream side portion of the boss-side camber line is larger than a curvature of an upstream side portion of the center-side camber line. An upstream end of the boss-side vane part is positioned on a side of a rotation direction of a runner in comparison with an upstream end of the center-side vane part when viewed toward a downstream side along a rotation axis line of the runner.
    Type: Application
    Filed: December 9, 2015
    Publication date: August 25, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Pohan KO, Koji HAMAGUCHI
  • Patent number: 8696125
    Abstract: An eye refractive power measurement apparatus includes: a measuring optical system for projecting measurement light onto a fundus of an examinee's eye, and causing a two-dimensional imaging device to capture the measurement light to be reflected from the fundus as a plurality of target pattern images at different distances from a measurement optical axis; a light deflecting member arranged at a position out of a conjugate position with a pupil of the examinee's eye on an optical path of the measuring optical system; a rotor for rotating the light deflecting member about an optical axis of the measuring optical system to allow a plurality of pattern light beams to be eccentrically rotated on the pupil; and a calculator for measuring an eye refractive power of the examinee's eye based on a target pattern image to be captured by the two-dimensional imaging device.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 15, 2014
    Assignee: Nidek Co., Ltd.
    Inventors: Koji Hamaguchi, Mitsuhiro Gono, Masaaki Hanebuchi, Hisashi Ochi
  • Publication number: 20120019778
    Abstract: An eye refractive power measurement apparatus includes: a measuring optical system for projecting measurement light onto a fundus of an examinee's eye, and causing a two-dimensional imaging device to capture the measurement light to be reflected from the fundus as a plurality of target pattern images at different distances from a measurement optical axis; a light deflecting member arranged at a position out of a conjugate position with a pupil of the examinee's eye on an optical path of the measuring optical system; a rotor for rotating the light deflecting member about an optical axis of the measuring optical system to allow a plurality of pattern light beams to be eccentrically rotated on the pupil; and a calculator for measuring an eye refractive power of the examinee's eye based on a target pattern image to be captured by the two-dimensional imaging device.
    Type: Application
    Filed: September 29, 2011
    Publication date: January 26, 2012
    Applicant: NIDEK CO., LTD.
    Inventors: Koji HAMAGUCHI, Mitsuhiro GONO, Masaaki HANEBUCHI, Hisashi OCHI
  • Patent number: 8079708
    Abstract: An eye refractive power measurement apparatus measures both eye refractive powers in cases where a pupil is small and large in diameter with ease. This apparatus includes: a measuring optical system causing an imaging device to capture a ring-shaped image based on measurement light reflected from a fundus of an examinee's eye; a light deflecting member arranged at a position, which is not conjugated with a pupil of the examinee's eye, on an optical path of the measuring optical system; a rotor causing the light deflecting member to rotate about an optical axis of the measuring optical system; and an eccentricity amount changer changing an amount of eccentricity of the measurement light, which is rotated eccentrically on a surface of the pupil, with respect to a center of the pupil, in order to change a region, where the measurement light passes, on the surface of the pupil.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: December 20, 2011
    Assignee: Nidek Co., Ltd.
    Inventors: Koji Hamaguchi, Mitsuhiro Gono
  • Publication number: 20110075097
    Abstract: An eye refractive power measurement apparatus measures both eye refractive powers in cases where a pupil is small and large in diameter with ease. This apparatus includes: a measuring optical system causing an imaging device to capture a ring-shaped image based on measurement light reflected from a fundus of an examinee's eye; a light deflecting member arranged at a position, which is not conjugated with a pupil of the examinee's eye, on an optical path of the measuring optical system; a rotor causing the light deflecting member to rotate about an optical axis of the measuring optical system; and an eccentricity amount changer changing an amount of eccentricity of the measurement light, which is rotated eccentrically on a surface of the pupil, with respect to a center of the pupil, in order to change a region, where the measurement light passes, on the surface of the pupil.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 31, 2011
    Applicant: NIDEK CO., LTD.
    Inventors: Koji HAMAGUCHI, Mitsuhiro GONO
  • Publication number: 20080212846
    Abstract: Tools and techniques for biometric authentication obtain a biologic information input such as a fingerprint image, which is to be accepted or rejected as being input from an authentic user. Calculated matching scores show respective degrees of similarity between the biologic information input and several templates. The templates include a fixed registration biologic information template, as well as non-fixed learning biologic information templates which are subject to replacement.
    Type: Application
    Filed: December 26, 2007
    Publication date: September 4, 2008
    Inventors: Kazuya Yamamoto, Shota Ichikawa, Koji Hamaguchi
  • Patent number: 7161207
    Abstract: A computer system comprising: (A) a CPU; (B) a memory arrangement comprising: (i) a side-wall memory array including a plurality of side-wall memory transistors; (ii) a charge pump; (iii) a plurality of switching circuits; and (iv) logic circuitry; and (C) a system bus, wherein each of the side-wall memory transistors comprises: a gate electrode formed on a semiconductor layer with a gate insulating film formed on the semiconductor layer; a channel region formed below the gate electrode; a pair of diffusion regions formed on the both sides of the channel region and having a conductive type opposite to that of the channel region; and a pair of memory functional units formed on the both sides of the gate electrode and having a function of retaining charges.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: January 9, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Koji Hamaguchi, Masaru Nawaki, Yoshinao Morikawa, Hiroshi Iwata, Akihide Shibata
  • Patent number: 7106630
    Abstract: A semiconductor storage device is provided, which comprises a memory array comprising a plurality of memory elements, a section for performing an erase or program operation with respect to the memory array, a section for receiving a suspend command, and in response to the suspend command, suspending the erase or program operation, and a section for receiving a resume command, and in response to the resume command, resuming the suspended erase or program operation. Each of the plurality of memory elements comprises a gate electrode provided via a gate insulating film on a semiconductor layer, a channel region provided under the gate electrode, diffusion regions provided on opposite sides of the channel region and having a conductivity type opposite to that of the channel region, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: September 12, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Koji Hamaguchi, Masaru Nawaki, Yoshinao Morikawa, Hiroshi Iwata, Akihide Shibata
  • Patent number: 7023731
    Abstract: A semiconductor memory device including: a memory cell array in which memory cells are arranged; a plurality of terminals for accepting commands issued by an external user; a command interface circuit for interfacing between the external user and the memory cell array; a write state machine for controlling the programming and erasing operations; and an output circuit for outputting an internal signal to the plurality of terminals, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: April 4, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Koji Hamaguchi, Masaru Nawaki, Yoshinao Morikawa, Hiroshi Iwata, Akihide Shibata
  • Patent number: 6998698
    Abstract: The present invention provides a memory cell having a variable resistor as a memory element, and also provides a memory device comprising the memory cells. The variable resistor is made of a thin-film material (for example, PCMO) or the like having a perovskite structure. So the memory cell can operate at a low voltage and can be highly integrated. The memory cell MC is formed of a combination of a current controlling device and a variable resistor. A field-effect transistor, diode or bipolar transistor is used as the current controlling device. The current controlling device is connected in series with the current path of the variable resistor so as to control a current flowing through the variable resistor.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: February 14, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Koji Inoue, Koji Hamaguchi
  • Patent number: 6977843
    Abstract: A semiconductor memory device has a malfunction prevention device and a nonvolatile memory. The nonvolatile memory is a memory cell including: a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed below the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having a function of retaining charges.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: December 20, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Koji Hamaguchi, Masaru Nawaki, Yoshinao Morikawa, Hiroshi Iwata, Akihide Shibata
  • Patent number: 6967867
    Abstract: A semiconductor memory device comprises a plurality of memory cells, each of which is capable of storing N-level data and being reprogrammed; and a plurality of monitor cells that separately store individual data values of the N-level data by using the same scheme as that used for the memory cells. Sensing means senses whether a physical quantity of the monitor cell which corresponds to the data value stored in the monitor cell is within a preset range; verification means verifies whether the physical quantity of the memory cell which corresponds to the data value stored in the memory cell is within the preset range when the sensing means has sensed that the physical quantity of the monitor cell is out of the preset range; correction means corrects the physical quantity.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: November 22, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Koji Hamaguchi
  • Patent number: 6862213
    Abstract: A semiconductor memory device comprises a memory cell formed of a nonvolatile resistance variable memory device in which a resistance value is variable according to the application of electrical stress, and a selection transistor; and word-line-voltage feeding means that feeds a word line voltage to a word line to be coupled to the memory cell. When executing a program operation for the memory cell and a verify operation for verifying a program state of the memory cell, the word-line-voltage feeding means feeds the word line voltage of the same voltage level to the word line to be coupled to the memory cell selected as a program target for two operations set as mutually related front and rear steps, namely, a program operation to be executed for the memory cell and a verify operation to be executed to verify a program state of the memory cell.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: March 1, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Koji Hamaguchi
  • Publication number: 20050002240
    Abstract: The present invention provides a semiconductor memory device including: a memory cell array in which memory cells are arranged; a plurality of terminals for accepting commands issued by an external user; a command interface circuit for interfacing between the external user and the memory cell array; a write state machine for controlling the programming and erasing operations; and an output circuit for outputting an internal signal to the plurality of terminals, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.
    Type: Application
    Filed: May 18, 2004
    Publication date: January 6, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Koji Hamaguchi, Masaru Nawaki, Yoshinao Morikawa, Hiroshi Iwata, Akihide Shibata
  • Publication number: 20040264257
    Abstract: A semiconductor storage device is provided, which comprises a memory array comprising a plurality of memory elements, a section for performing an erase or program operation with respect to the memory array, a section for receiving a suspend command, and in response to the suspend command, suspending the erase or program operation, and a section for receiving a resume command, and in response to the resume command, resuming the suspended erase or program operation. Each of the plurality of memory elements comprises a gate electrode provided via a gate insulating film on a semiconductor layer, a channel region provided under the gate electrode, diffusion regions provided on opposite sides of the channel region and having a conductivity type opposite to that of the channel region, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.
    Type: Application
    Filed: May 20, 2004
    Publication date: December 30, 2004
    Inventors: Koji Hamaguchi, Masaru Nawaki, Yoshinao Morikawa, Hiroshi Iwata, Akihide Shibata