Patents by Inventor Koji Izunome
Koji Izunome has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11887845Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.Type: GrantFiled: September 29, 2021Date of Patent: January 30, 2024Assignees: GLOBALWAFERS JAPAN CO., LTD., TOHOKU UNIVERSITYInventors: Kazutaka Kamijo, Etsuo Fukuda, Takashi Ishikawa, Koji Izunome, Moriya Miyashita, Takao Sakamoto, Tetsuo Endoh
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Publication number: 20230243062Abstract: A silicon wafer is provided which is a Czochralski wafer formed of silicon, and a method for producing the silicon wafer are provided. The wafer includes a bulk layer having an oxygen concentration of 0.5×1018/cm3 or more; and a surface layer extending from the surface of the wafer to 300 nm in depth, and having an oxygen concentration of 2×1018/cm3 or more.Type: ApplicationFiled: June 14, 2021Publication date: August 3, 2023Inventors: Haruo SUDO, Takashi ISHIKAWA, Koji IZUNOME, Hisashi MATSUMURA, Tatsuhiko AOKI, Shoji IKEDA, Tetsuo ENDOH, Etsuo FUKUDA
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Publication number: 20220093396Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.Type: ApplicationFiled: September 29, 2021Publication date: March 24, 2022Applicants: GLOBALWAFERS JAPAN CO., LTD., TOHOKU UNIVERSITYInventors: Kazutaka KAMIJO, Etsuo FUKUDA, Takashi ISHIKAWA, Koji IZUNOME, Moriya MIYASHITA, Takao SAKAMOTO, Tetsuo ENDOH
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Publication number: 20200211840Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.Type: ApplicationFiled: July 17, 2018Publication date: July 2, 2020Applicants: GlobalWafers Japan Co., Ltd., TOHOKU UNIVERSITYInventors: Kazutaka KAMIJO, Etsuo FUKUDA, Takashi ISHIKAWA, Koji IZUNOME, Moriya MIYASHITA, Takao SAKAMOTO, Tetsuo ENDOH
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Patent number: 8999864Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.Type: GrantFiled: May 28, 2010Date of Patent: April 7, 2015Assignee: Global Wafers Japan Co., Ltd.Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
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Patent number: 8476149Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.Type: GrantFiled: July 30, 2009Date of Patent: July 2, 2013Assignee: Global Wafers Japan Co., Ltd.Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Yoichiro Mochizuki, Akihiko Kobayashi, Senlin Fu
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Patent number: 8399341Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.Type: GrantFiled: May 17, 2010Date of Patent: March 19, 2013Assignee: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Patent number: 8252700Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.Type: GrantFiled: January 21, 2010Date of Patent: August 28, 2012Assignee: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Publication number: 20120184091Abstract: The invention is to provide a method for heat treating a silicon wafer reducing grown-in defects while suppressing generation of slip during RTP and improving surface roughness of the wafer. The method performing a first heat treatment while introducing a rare gas, the first heat treatment comprising the steps of rapidly heating the wafer to T1 of 1300° C. or higher and the melting point of silicon or lower, keeping the wafer at T1, rapidly cooling the wafer to T2 of 400-800° C. and keeping the wafer at T2; and performing a second heat treatment while introducing an oxygen gas in an amount of 20-100 vol. %, the second heat treatment comprising the steps of keeping the wafer at T2, rapidly heating the wafer from T2 to T3 of 1250° C. or higher and the melting point of silicon or lower, keeping the wafer at T3 and rapidly cooling the wafer.Type: ApplicationFiled: May 17, 2010Publication date: July 19, 2012Applicant: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Publication number: 20120139088Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.Type: ApplicationFiled: May 28, 2010Publication date: June 7, 2012Applicant: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
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Patent number: 7977219Abstract: In a manufacturing method for a silicon wafer, a first heat treatment process is performed on the silicon wafer while introducing a first gas having an oxygen gas in an amount of 0.01 vol. % or more and 1.00 vol. % or less and a rare gas, and a second heat treatment process is performed while stopping introducing the first gas and introducing a second gas having an oxygen gas in an amount of 20 vol. % or more and 100 vol. % or less and a rare gas. In the first heat treatment process, the silicon wafer is rapidly heated to first temperature of 1300° C. or higher and a melting point of silicon or lower at a first heating rate, and kept at the first temperature. In the second heat treatment process, the silicon wafer is kept at the first temperature, and rapidly cooled from the first temperature at a first cooling rate.Type: GrantFiled: July 30, 2009Date of Patent: July 12, 2011Assignee: Covalent Materials CorporationInventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Publication number: 20100197146Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.Type: ApplicationFiled: January 21, 2010Publication date: August 5, 2010Applicant: COVALENT MATERIALS CORPORATIONInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Patent number: 7679730Abstract: An image pickup device disposed in a predetermined position relative to a surface of a strained silicon wafer photographs the surface of the strained silicon wafer in a plurality of rotation angle positions on photographing conditions under which bright lines appearing on the surface of the strained silicon wafer can be photographed, in an environment where a light source device illuminates the surface of the strained silicon wafer which is rotating. A composite image in a predetermined angle position is generated from surface images of the strained silicon wafer in a plurality of rotation angle positions obtained by the image pickup device.Type: GrantFiled: September 13, 2007Date of Patent: March 16, 2010Assignees: Shibaura Mechatronics Corporation, Covalent Materials CorporationInventors: Hideaki Takano, Miyuki Shimizu, Takeshi Senda, Koji Izunome, Yoshinori Hayashi, Kazuhiko Hamatani
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Publication number: 20100055884Abstract: In a manufacturing method for a silicon wafer, a first heat treatment process is performed on the silicon wafer while introducing a first gas having an oxygen gas in an amount of 0.01 vol. % or more and 1.00 vol. % or less and a rare gas, and a second heat treatment process is performed while stopping introducing the first gas and introducing a second gas having an oxygen gas in an amount of 20 vol. % or more and 100 vol. % or less and a rare gas. In the first heat treatment process, the silicon wafer is rapidly heated to first temperature of 1300° C. or higher and a melting point of silicon or lower at a first heating rate, and kept at the first temperature. In the second heat treatment process, the silicon wafer is kept at the first temperature, and rapidly cooled from the first temperature at a first cooling rate.Type: ApplicationFiled: July 30, 2009Publication date: March 4, 2010Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Publication number: 20100038757Abstract: A silicon wafer produced from a silicon single crystal ingot grown by Czochralski process is subjected to rapid heating/cooling thermal process at a maximum temperature (T1) of 1300° C. or more, but less than 1380° C. in an oxidizing gas atmosphere having an oxygen partial pressure of 20% or more, but less than 100%. The silicon wafer according to the invention has, in a defect-free region (DZ layer) including at least a device active region of the silicon wafer, a high oxygen concentration region having a concentration of oxygen solid solution of 0.7×1018 atoms/cm3 or more and at the same time, the defect-free region contains interstitial silicon in supersaturated state.Type: ApplicationFiled: July 30, 2009Publication date: February 18, 2010Inventors: Hiromichi Isogai, Takeshi Senda, Eiji Toyoda, Kumiko Murayama, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Yoichiro Mochizuki, Akihiko Kobayashi, Senlin Fu
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Publication number: 20090066933Abstract: An image pickup device disposed in a predetermined position relative to a surface of a strained silicon wafer photographs the surface of the strained silicon wafer in a plurality of rotation angle positions on photographing conditions under which bright lines appearing on the surface of the strained silicon wafer can be photographed, in an environment where a light source device illuminates the surface of the strained silicon wafer which is rotating. A composite image in a predetermined angle position is generated from surface images of the strained silicon wafer in a plurality of rotation angle positions obtained by the image pickup device.Type: ApplicationFiled: March 27, 2006Publication date: March 12, 2009Applicants: SHIBAURA MECHATRONICS CORPORATION, COVALENT MATERIALS CORPORATIONInventors: Hideaki Takano, Miyuki Shimizu, Takeshi Sendia, Koji Izunome, Yoshinori Hayashi, Kazuhiko Hamatani
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Publication number: 20090004825Abstract: A method of manufacturing a semiconductor substrate having a DSB structure that enables simplification of a manufacturing process by optimizing a total thickness of oxides on surfaces of two wafers before being bonded together is provided. The method comprises a process of preparing a first semiconductor wafer and a second semiconductor wafer, a process of bonding the first semiconductor wafer and second semiconductor wafer when a total of thickness of an oxide on the surface of the first semiconductor wafer and that of an oxide on the surface of the second semiconductor wafer is 0.4 nm or more and 1.0 nm or less, and a process of providing heat treatment to a semiconductor substrate after the process of the bonding and before a process of thinning one of the wafers.Type: ApplicationFiled: January 4, 2008Publication date: January 1, 2009Applicant: Covalent Materials CorporationInventors: Takeshi SENDA, Hiromichi ISOGAI, Eiji TOYODA, Akiko NARITA, Koji IZUNOME
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Patent number: 7403278Abstract: A surface inspection apparatus, for inspecting a plurality of surfaces formed in a peripheral edge portion of a plate-like object, includes a image pickup mechanism, which photographs the peripheral edge portion of the plate-like object having a plurality of surfaces, and an image processing device, which processes an image obtained by the photographing device. The image pickup mechanism includes an optical system which guides images of the plurality of surfaces of the plate-like object in one direction, and a camera unit having an image pickup surface, on which the images of the plurality of surfaces guided by the optical system in the one direction are formed.Type: GrantFiled: May 29, 2007Date of Patent: July 22, 2008Assignees: Shibaura Mechatronics Corporation, Covalent Materials CorporationInventors: Yoshinori Hayashi, Hiroyuki Naraidate, Makoto Kyoya, Koji Izunome, Hiromi Nagahama, Miyuki Shimizu, Kazuhiko Hamatani
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Publication number: 20080166891Abstract: The present invention provides a heat treatment method for a silicon wafer in which, with respect to a surface of the silicon wafer made flat at an atomic level by a high-temperature heat-treatment at 1,100° C. or more, a surface roughness of the wafer can be reduced compared with the conventional one while maintaining a step terrace structure on the surface of the above-mentioned wafer, and the surface of such a wafer can be formed stably. In the heat treatment method for the silicon wafer in which the step terrace structure is formed on the surface of the silicon wafer, after the silicon wafer is heat treated at 1,100° C. or more in a heat treatment furnace in a reducing gas or inert gas atmosphere, the atmosphere in the furnace is arranged to be of argon gas at a temperature of 500° C.Type: ApplicationFiled: December 27, 2007Publication date: July 10, 2008Inventors: Manabu Hirasawa, Koji Izunome, Koji Araki, Tatsuhiko Aoki
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Publication number: 20080164572Abstract: A semiconductor substrate whose surface roughness is reduced by optimizing an inclination (off angle) with respect to a {110} surface of the semiconductor substrate surface and a manufacturing method thereof are provided. The surface of the semiconductor substrate has the inclination (off angle) of 0 degree or more and 0.12 degrees or less, or 5 degrees or more and 11 degrees or less, preferably 6 degrees or more and 9 degrees or less with respect to the {110} surface. The manufacturing method of a semiconductor substrate has a process in which a semiconductor single crystal ingot is sliced at an inclination (off angle) of 5 degrees or more and 11 degrees or less, preferably 6 degrees or more and 9 degrees or less with respect to the {110} surface.Type: ApplicationFiled: December 19, 2007Publication date: July 10, 2008Applicant: Covalent Materials CorporationInventors: Eiji Toyoda, Takeshi Senda, Akiko Narita, Hiromichi Isogai, Koji Izunome