Patents by Inventor Koji Izunome
Koji Izunome has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070240628Abstract: Provided is a silicon wafer suitable for manufacturing a semiconductor device having a shallow junction. A silicon wafer wherein, in a region at a depth of less than 50 ?m from a surface, a density of oxygen deposition materials each having a diameter of not less than 10 nm is not more than 1×108/cm3. A silicon wafer for a semiconductor device, which is manufactured by applying heat treatment at a heat treatment temperature of not less than 1000° C. for heat treatment time of not more than 3 msec, wherein, in a region at a depth of less than 50 ?m from a surface, a density of oxygen deposition materials each having a diameter of not less than 10 nm is not more than 1×108/cm3.Type: ApplicationFiled: April 5, 2007Publication date: October 18, 2007Applicant: Toshiba Ceramics Co., LtdInventors: Takashi Watanabe, Hiroyuki Saito, Takeshi Senda, Koji Izunome, Kazuhiko Kashima
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Publication number: 20070222977Abstract: A surface inspection apparatus, for inspecting a plurality of surfaces formed in a peripheral edge portion of a plate-like object, includes a image pickup mechanism, which photographs the peripheral edge portion of the plate-like object having a plurality of surfaces, and an image processing device, which processes an image obtained by the photographing device. The image pickup mechanism includes an optical system which guides images of the plurality of surfaces of the plate-like object in one direction, and a camera unit having an image pickup surface, on which the images of the plurality of surfaces guided by the optical system in the one direction are formed.Type: ApplicationFiled: May 29, 2007Publication date: September 27, 2007Applicants: SHIBAURA MECHATRONICS CORPORATION, TOSHIBA CERAMICS CO., LTD.Inventors: Yoshinori Hayashi, Hiroyuki Naraidate, Makoto Kyoya, Koji Izunome, Hiromi Nagahama, Miyuki Shimizu, Kazuhiko Hamatani
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Patent number: 7250357Abstract: A manufacturing method for producing a stained silicon wafer has the steps of forming an Si1-xGex composition-graded layer of which Ge concentration is stepwisely increased on a single crystal silicon substrate, forming an Si1-xGex uniform composition layer of which Ge concentration is constant on the Si1-xGex composition-graded layer, forming a stain-relaxed Si1-yGey layer of which Ge concentration y is constant while y satisfies relationship of 0.5x?y<x on the Si1-xGex uniform composition layer and epitaxially growing a strained Si layer on the strain-relaxed Si1-yGey layer.Type: GrantFiled: September 8, 2005Date of Patent: July 31, 2007Assignee: Toshiba Ceramics Co., Ltd.Inventors: Takeshi Senda, Koji Izunome
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Patent number: 7247583Abstract: A method for manufacturing a strained silicon wafer, having steps of a first step of preparing a single crystal silicon substrate, a second step of forming a graded SiGe layer on the substrate, the graded SiGe layer having a first Ge composition ratio increased stepwisely from 5 to 60% at atomic ratio, a third step of forming a SiGe constant composition layer on the graded SiGe layer, the SiGe constant composition layer having a Ge composition ratio substantially equal to the Ge composition ratio on a surface of the-graded SiGe layer and a fourth step of forming a strained Si layer on the SiGe constant composition layer. The second through fourth steps are performed under the reduced pressure atmosphere while the single crystal silicon substrate is rotated in a circumferential direction at a rate from 300 rpm to 1500 rpm.Type: GrantFiled: January 21, 2005Date of Patent: July 24, 2007Assignee: Toshiba Ceramics Co., Ltd.Inventors: Hisatsugu Kurita, Masato Igarashi, Takeshi Senda, Koji Izunome
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Publication number: 20070068447Abstract: In order to control a crystal defective area, to inhibit slip generation at the time of annealing treatment, and to manufacture a high quality silicon wafer of high strength with sufficient yields, a method of manufacturing a silicon wafer is provided in which a silicon single crystal is grown by way of Czochralski method under conditions where an oxygen concentration is 0.9×1018 atoms/cm3 or more and an oxidization induced stacking fault density is the maximum in an area within 20 mm of a wafer circumference, and an as-grown defect density of the wafer obtained by slicing the silicon single crystal is 1×107/cm3 or more over the whole region of the wafer.Type: ApplicationFiled: September 26, 2006Publication date: March 29, 2007Inventors: Koji Izunome, Yumiko Hirano, Takashi Watanabe, Kazuhiko Kashima, Hiroyuki Saito, Takeshi Senda
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Patent number: 7193294Abstract: A semiconductor substrate includes a support substrate 1 has gettering sites 10 for gettering impurity metal, an embedded insulating film 2 which is provided on the support substrate 1 and contains oxides of an element whose single bond energy to oxygen is higher than that to silicon, and a semiconductor layer (an SOI layer) 3 provided on the embedded insulating film 2.Type: GrantFiled: December 3, 2004Date of Patent: March 20, 2007Assignee: Toshiba Ceramics Co., Ltd.Inventors: Reiko Yoshimura, Tsukasa Tada, Koji Izunome, Kazuhiko Kashima
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Patent number: 7149341Abstract: A wafer inspection apparatus has a supporting means (10) for rotatably supporting a wafer (W) formed of a disk, a circumferential edge imaging means (40) for imaging a circumferential edge (S) of the wafer (W) that is supported by the supporting means for rotation, a notch imaging means (50) for imaging a notch (N), a notch illumination part (52) for illuminating the notch (N), and a control means (70) for processing image data imaged by the circumferential edge imaging means (40) and the notch imaging means (50). The circumferential edge imaging means (40) has a plurality of imaging cameras (41) for imaging a plurality of different parts in a thickness direction of the circumferential edge of the wafer (W). The different parts of the circumferential edge (S) of the wafer (W) include an apex at right angles to a surface of the wafer (W) and a front side bevel and a back side bevel inclined relative to the apex.Type: GrantFiled: February 11, 2003Date of Patent: December 12, 2006Assignees: Toshiba Ceramics Co., Ltd., Shibaura Mechatronics CorporationInventors: Yoshinori Hayashi, Hiroyuki Naraidate, Hiroaki Yuda, Atsushi Tanabe, Hiromichi Isogai, Koji Izunome
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Patent number: 7060597Abstract: A manufacturing method for a silicon substrate having a strained layer, has steps of forming a plurality of atomic steps having a height of 0.1 nm or more on the surface of a silicon substrate, forming a plurality of terraces having a width of 0.1 ?m or more between the plurality of atomic steps and forming a SiGe layer or a SiGe layer and a Si layer on the silicon substrate.Type: GrantFiled: May 18, 2004Date of Patent: June 13, 2006Assignee: Toshiba Ceramics Co., Ltd.Inventors: Hisatsugu Kurita, Masato Igarashi, Takeshi Senda, Koji Izunome
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Publication number: 20060118868Abstract: A semiconductor substrate includes a support substrate 1 has gettering sites 10 for gettering impurity metal, an embedded insulating film 2 which is provided on the support substrate 1 and contains oxides of an element whose single bond energy to oxygen is higher than that to silicon, and a semiconductor layer (an SOI layer) 3 provided on the embedded insulating film 2.Type: ApplicationFiled: December 3, 2004Publication date: June 8, 2006Inventors: Reiko Yoshimura, Tsukasa Tada, Koji Izunome, Kazuhiko Kashima
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Publication number: 20060057856Abstract: A manufacturing method for producing a stained silicon wafer has the steps of forming an Si1-xGex composition-graded layer of which Ge concentration is stepwisely increased on a single crystal silicon substrate, forming an Si1-xGex uniform composition layer of which Ge concentration is constant on the Si1-xGex composition-graded layer, forming a stain-relaxed Si1-yGey layer of which Ge concentration y is constant while y satisfies relationship of 0.5x?y<x on the Si1-xGex uniform composition layer and epitaxially growing a strained Si layer on the strain- relaxed Si1-yGey layer.Type: ApplicationFiled: September 8, 2005Publication date: March 16, 2006Inventors: Takeshi Senda, Koji Izunome
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Publication number: 20050170664Abstract: A method for manufacturing a strained silicon wafer, having steps of a first step of preparing a single crystal silicon substrate, a second step of forming a graded SiGe layer on the substrate, the graded SiGe layer having a first Ge composition ratio increased stepwisely from 5 to 60% at atomic ratio, a third step of forming a SiGe constant composition layer on the graded SiGe layer, the SiGe constant composition layer having a Ge composition ratio substantially equal to the Ge composition ratio on a surface of the-graded SiGe layer and a fourth step of forming a strained Si layer on the SiGe constant composition layer. The second through fourth steps are performed under the reduced pressure atmosphere while the single crystal silicon substrate is rotated in a circumferential direction at a rate from 300 rpm to 1500 rpm.Type: ApplicationFiled: January 21, 2005Publication date: August 4, 2005Inventors: Hisatsugu Kurita, Masato Igarashi, Takeshi Senda, Koji Izunome
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Publication number: 20040235274Abstract: A manufacturing method for a silicon substrate having a strained layer, has steps of forming a plurality of atomic steps having a height of 0.1 nm or more on the surface of a silicon substrate, forming a plurality of terraces having a width of 0.1 &mgr;m or more between the plurality of atomic steps and forming a SiGe layer or a SiGe layer and a Si layer on the silicon substrate.Type: ApplicationFiled: May 18, 2004Publication date: November 25, 2004Applicant: TOSHIBA CERAMICS CO., LTD.Inventors: Hisatsugu Kurita, Masato Igarashi, Takeshi Senda, Koji Izunome
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Publication number: 20030169916Abstract: A wafer inspection apparatus has a supporting means (10) for rotatably supporting a wafer (W) formed of a disk, a circumferential edge imaging means (40) for imaging a circumferential edge (S) of the wafer (W) that is supported by the supporting means for rotation, a notch imaging means (50) for imaging a notch (N), a notch illumination part (52) for illuminating the notch (N), and a control means (70) for processing image data imaged by the circumferential edge imaging means (40) and the notch imaging means (50). The circumferential edge imaging means (40) has a plurality of imaging cameras (41) for imaging a plurality of different parts in a thickness direction of the circumferential edge of the wafer (W). The different parts of the circumferential edge (S) of the wafer (W) include an apex at right angles to a surface of the wafer (W) and a front side bevel and a back side bevel inclined relative to the apex.Type: ApplicationFiled: February 11, 2003Publication date: September 11, 2003Applicant: TOSHIBA CERAMICS CO., LTD.Inventors: Yoshinori Hayashi, Hiroyuki Naraidate, Hiroaki Yuda, Atsushi Tanabe, Hiromichi Isogai, Koji Izunome
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Patent number: 5704974Abstract: When a Si single crystal 8 is pulled up from a melt 6 received in a crucible 2, the state of eddy flows generated in the melt 6 is judged from the temperature distribution of the melt at the surface. According to the result of judgement, the gas, i.e. N.sub.2, Xe or Kr, which causes extraoridnary deviation in the density of a melt 6 is added to an atmospheric gas, so as to keep the eddy flows under unstabilized condition. The effect of said gas is typical in the case of crystal growth from the melt to which a dopant such as Ca, Sb, Al, As or In having the effect to suppress the extraordinary deviation in the density is added. Since the single crystal is pulled up from the melt held in the temperature-controlled condition at the surface, impurity distribution and oxygen distribution are made uniform along the direction of crystal growth. A single crystal obtained in this way has highly-stabilized quality.Type: GrantFiled: March 22, 1996Date of Patent: January 6, 1998Assignees: Research Development Corporation of Japan, Sumitomo Sitix Corporation, Toshiba Ceramics Co., Ltd., Nippon Steel Corporation, Komatsu Electronic Metals Co., Ltd., Mitsubishi Materials CorporationInventors: Koji Izunome, Souroku Kawanishi, Shinji Togawa, Atsushi Ikari, Hitoshi Sasaki, Shigeyuki Kimura
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Patent number: 5700320Abstract: When a B or P-doped Si single crystal is pulled up from a B or P-doped melt by the Czochralski method, an element such as Ga, Sb or In having the effect to reduce the heat expansion coefficient of said melt at a temperature near the melting point is added to said melt. The additive element stabilizes the temperature condition of crystal growth so as to control the generation of eddy flows just below the interface of crystal growth.When a Ga or Sb-doped Si single crystal is pulled up from a Ga or Sb-doped melt, an element such as B or P having the effect to increase the heat expansion coefficient of said melt at a temperature near the melting point is added. The agitation of the melt just below the interface of crystal growth is accelerated by the addition of B or P, so as to assure the growth of a Si single crystal from the melt having impurity distribution made uniform along the radial direction.Type: GrantFiled: March 22, 1996Date of Patent: December 23, 1997Assignees: Research Development Corporation of Japan, Sumitomo Sitix Corporation, Toshiba Ceramics Co., Ltd., Nippon Steel Corporation, Komatsu Electronic Metals Co., Ltd., Mitsubishi Materials CorporationInventors: Koji Izunome, Souroku Kawanishi, Shinji Togawa, Atsushi Ikari, Hitoshi Sasaki, Shigeyuki Kimura
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Patent number: 5683504Abstract: When a single crystal is pulled up from a melt, the difference .DELTA.T between temperatures at the bottom of a crucible and at the interface of crystal growth is controlled so as to hold the Rayleigh constant defined by the formula of:R a=g.multidot..beta..multidot..DELTA.T.multidot.L/.kappa..multidot..nu.within the range of 5.times.10.sup.5 -4.times.10.sup.7, wherein g represents the acceleration of gravity, .beta. the volumetric expansion coefficient of the melt, L the depth of the melt, .kappa. thermal diffusivity and .nu. the kinematic viscocity. Since the convection mode of the melt at the interface of crystal growth is constantly held in the region of soft turbulence, a single crystal is grown under the stabilized temperature condition without the transfer of the impurity distribution in the melt into the growing single crystal.Type: GrantFiled: March 22, 1996Date of Patent: November 4, 1997Assignees: Research Development Corporation of Japan, Sumitomo Sitix Corporation, Toshiba Ceramics Co., Ltd., Nippon Steel Corporation, Komatsu Electronic Metals Co., Ltd., Mitsubishi Materials CorporationInventors: Koji Izunome, Souroku Kawanishi, Shinji Togawa, Atsushi Ikari, Hitoshi Sasaki, Shigeyuki Kimura
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Patent number: 5477805Abstract: A Si material mixed with Group-V element is melted in a crucible, and then held in a chamber filled with a rare gas at atmospheric pressure of 100 torr. or higher. A rare gas, e.g. Ar, Kr, Xe or Rn, having a large mass or the mixture of Ar with Kr, Xe or Rn may be used as atmospheric gas. The high-pressure atmosphere suppress the evaporation of oxides of Group-V elements from the Si melt, so that the Si melt can be maintained at a high oxygen concentration under a stable condition until the start of pulling operation.Type: GrantFiled: December 7, 1994Date of Patent: December 26, 1995Assignees: Research Development Corporation of Japan, Koji Izunome, Kazutaka TerashimaInventors: Koji Izunome, Xin ming Huang, Kazutaka Terashima, Shigeyuki Kimura