Abstract: A sensor chip of a magnetic sensor includes a magnetosensitive element, ferromagnetic films forming a magnetic gap overlapping the magnetosensitive element, and a passivation film provided on the ferromagnetic films so as to be filled in the magnetic gap. The ferromagnetic films each include a lower magnetic film and an upper magnetic film. The magnetic gap is configured such that a width between the upper magnetic films is larger than a width between the lower magnetic films. The material of the lower magnetic film is higher in permeability than the material of the upper magnetic film. With the above configuration, magnetic flux is efficiently applied to the magnetosensitive element, making it possible to achieve high detection sensitivity.

Abstract: A magnetic sensor has a magnetoresistive strip including a plurality of magnetoresistive elements arranged in the y-direction through a plurality of hard magnetic members and ferromagnetic films arranged in the x-direction through a magnetic gap. The magnetoresistive strip is disposed around a magnetic gap. One end of the magnetoresistive strip in the y-direction is connected to a terminal electrode not through another magnetoresistive element applied with another magnetic field to be detected, and the other end thereof in the y-direction is connected to a terminal electrode not through another magnetoresistive element applied with the magnetic field to be detected. The magnetoresistive strip S thus has a linear shape not having a folded structure, so that the relation between the direction of a magnetic bias and the direction of flow of current becomes constant over all the sections of the magnetoresistive strip.

Abstract: To increase, in a magnetic sensor having a magnetoresistive strip and a ferromagnetic film, a magnetic bias to be applied to a magnetoresistive element by magnetically coupling the magnetoresistive strip and ferromagnetic film. A magnetic sensor 1 includes a magnetoresistive strip S, an insulating film 13 that covers the magnetoresistive strip S, and ferromagnetic films M1 and M2 formed on the insulating film 13 and arranged in the x-direction through a magnetic gap G extending in the y-direction. The ferromagnetic films M1 and M2 overlap a plurality of hard magnetic members H through the insulating film 13. This allows two adjacent hard magnetic members H to be magnetically coupled through the ferromagnetic films M1 and M2. This makes it possible to increase the magnetic bias to be applied to a magnetoresistive element R without involving an increase in the size of the hard magnetic member H.

Abstract: A magnetic sensor has a magnetoresistive strip including a plurality of magnetoresistive elements arranged in the y-direction through a plurality of hard magnetic members and ferromagnetic films arranged in the x-direction through a magnetic gap. The magnetoresistive strip is disposed around a magnetic gap. One end of the magnetoresistive strip in the y-direction is connected to a terminal electrode not through another magnetoresistive element applied with another magnetic field to be detected, and the other end thereof in the y-direction is connected to a terminal electrode not through another magnetoresistive element applied with the magnetic field to be detected. The magnetoresistive strip S thus has a linear shape not having a folded structure, so that the relation between the direction of a magnetic bias and the direction of flow of current becomes constant over all the sections of the magnetoresistive strip.

Abstract: A semiconductor device includes a first signal wiring, a first dummy wiring, and a second dummy wiring. The first signal wiring is configured to be supplied with a first signal potential. The first dummy wiring is insulated from the first wiring. The first dummy wiring is configured to be supplied with a fixed potential. The second dummy wiring is disposed between the first signal wiring and the first dummy wiring. The second dummy wiring is insulated from the first dummy wiring. The second dummy wiring is configured to be supplied with substantially the same potential as the first signal potential.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip including a first circuit, a second circuit, a first interconnect connected to the first circuit, a second interconnect connected to the second circuit, and a third interconnect connecting the first interconnect and the second interconnect.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip including a first circuit, a second circuit, a first interconnect connected to the first circuit, a second interconnect connected to the second circuit, and a third interconnect connecting the first interconnect and the second interconnect.

Abstract: According to an embodiment, a semiconductor device includes a first pull-up driver, a first pull-down driver, a second pull-up driver and a second pull-down driver. The first pull-up driver is configured to pull up a voltage of a signal output terminal, whose ON resistance is capable of being adjusted to a predetermined reference resistance value. The first pull-down driver is configured to pull down the voltage of the signal output terminal, whose ON resistance is capable of being adjusted to the reference resistance value. The second pull-up driver is configured to pull up the voltage of the signal output terminal, whose ON resistance is capable of being adjusted to n times the reference resistance value. The second pull-down driver is configured to pull down the voltage of the signal output terminal, whose ON resistance is capable of being adjusted to the n times the reference resistance value.

Abstract: A method for comparing phases between first and second clock signal includes the first clock signals to a first precharge circuit coupled between a first node and a first terminal to which a first voltage is applied. The first clock signal is supplied to a second precharge circuit coupled between a second node and the first terminal. The second clock signal is supplied to a first discharge circuit coupled between the first node and a second terminal to which a second voltage different from the first voltage is applied. The second clock signal is supplied to a second discharge circuit coupled between the second node and the second terminal.

Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. An equalizing circuit precharges/equalizes the two sense nodes.

Abstract: In one embodiment, to maintain the operation stability of a semiconductor device even when an external voltage changes. An input signal discrimination unit operates with a power supply potential supplied from a first power supply line VDDI. The input signal discrimination unit compares an input signal VIN with a reference potential Vref. The comparison result is inverted into a signal V0 by an inverter INV1. A power supply sensor circuit monitors the potential of the first power supply line VDDI. If an external potential VDDI falls below a reference potential VX, the power supply sensor circuit turns on a second current source. When the second current source is turned on, an operating current is supplied to a discrimination unit from the second current source as well as a first current source.

Abstract: To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.

Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. An equalizing circuit precharges/equalizes the two sense nodes.

Abstract: To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.

Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 2).

Abstract: A level shift circuit includes: a pair of first and second P-channel transistors which are connected in a flip-flop manner and whose sources connected to a first power supply line; a pair of first and second N-channel transistors with the first N-channel transistor provided between the first P-channel transistor and a second power supply line and the second N-channel transistor provided between the second P-channel transistor and the second power supply line, in which input signals complementary to each other are inputted to their gates; and a current supply circuit provided between the first power supply line and a drain of the first N-channel transistor and between the first power supply line and a drain of the second N-channel transistor, respectively.

Abstract: To suppress the number of clocks needed to adjust the impedance of an output buffer. A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and is controlled in impedance by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and is controlled in impedance by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values. The impedances of the replica buffers are increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.

Abstract: A semiconductor device includes a first power supply terminal, a second power supply terminal, and first and second capacitors. The first power supply terminal is configured to be supplied with a first electrical potential. The second power supply terminal is configured to be supplied with a second electrical potential. The second electrical potential is different from the first electrical potential. The first and second capacitors are coupled in series between the first and second power supply terminals.

Abstract: A semiconductor device includes a first signal wiring, a first dummy wiring, and a second dummy wiring. The first signal wiring is configured to be supplied with a first signal potential. The first dummy wiring is insulated from the first wiring. The first dummy wiring is configured to be supplied with a fixed potential. The second dummy wiring is disposed between the first signal wiring and the first dummy wiring. The second dummy wiring is insulated from the first dummy wiring. The second dummy wiring is configured to be supplied with substantially the same potential as the first signal potential.

Abstract: A DLL circuit is designed to adjust the delay time and the duty applied to an input clock signal, thus producing a DLL clock signal. In a non-clocking state of the DLL clock signal in which pulses disappear temporarily, the DLL circuit stops updating the delay time and the duty of the DLL clock signal. That is, the DLL circuit is capable of preventing a phase difference between the input clock signal and the DLL clock signal from being erroneously detected in the non-clocking state of the DLL clock signal, thus preventing the delay time and the duty from being updated based on the erroneously detected phase difference. Thus, it is possible to reduce the number of cycles adapted to the delay-locked control and to thereby stabilize the operation of the DLL circuit.