Abstract: To provide a semiconductor memory device including: a first clock generation circuit and a second clock generation circuit that generate a first internal clock and a second internal clock, respectively; a latency counter that counts latency synchronously with the first internal clock; and a recovery counter that counts a write recovery period synchronously with the second internal clock. The second clock generation circuit activates the second internal clock when auto-precharge is designated, and deactivates the second internal clock when the auto-precharge is not designated. With this configuration, the recovery counter does not perform any counting operation when an auto-precharge function is not operated, and thus unnecessary power consumption can be prevented.

Abstract: A level shift circuit includes: a pair of first and second P-channel transistors which are connected in a flip-flop manner and whose sources connected to a first power supply line; a pair of first and second N-channel transistors with the first N-channel transistor provided between the first P-channel transistor and a second power supply line and the second N-channel transistor provided between the second P-channel transistor and the second power supply line, in which input signals complementary to each other are inputted to their gates; and a current supply circuit provided between the first power supply line and a drain of the first N-channel transistor and between the first power supply line and a drain of the second N-channel transistor, respectively.

Abstract: In one embodiment, to maintain the operation stability of a semiconductor device even when an external voltage changes. An input signal discrimination unit operates with a power supply potential supplied from a first power supply line VDDI. The input signal discrimination unit compares an input signal VIN with a reference potential Vref. The comparison result is inverted into a signal V0 by an inverter INV1. A power supply sensor circuit monitors the potential of the first power supply line VDDI. If an external potential VDDI falls below a reference potential VX, the power supply sensor circuit turns on a second current source. When the second current source is turned on, an operating current is supplied to a discrimination unit from the second current source as well as a first current source.

Abstract: A DLL circuit is designed to adjust the delay time and the duty applied to an input clock signal, thus producing a DLL clock signal. In a non-clocking state of the DLL clock signal in which pulses disappear temporarily, the DLL circuit stops updating the delay time and the duty of the DLL clock signal. That is, the DLL circuit is capable of preventing a phase difference between the input clock signal and the DLL clock signal from being erroneously detected in the non-clocking state of the DLL clock signal, thus preventing the delay time and the duty from being updated based on the erroneously detected phase difference. Thus, it is possible to reduce the number of cycles adapted to the delay-locked control and to thereby stabilize the operation of the DLL circuit.

Abstract: A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage.

Abstract: In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 2).

Abstract: A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. Further, the row address decoder selects the redundant word line when a replacement signal is received. A column decoder selects the bit lines in response to a column address. A row address redundancy circuit stores a redundant row address. The row address redundancy circuit provides the replacement signal when the redundant row address corresponds to the received address. The mode setting circuit receives a mode signal having a normal mode and a test mode. The mode setting circuit outputs the replacement signal to the row decoder when the mode signal is in the normal mode, and prohibits an output of the replacement signal.

Abstract: A calibration circuit includes: a replica buffer that drives a calibration terminal ZQ; a reference voltage generating circuit that generates a reference voltage VMID; a comparing circuit that compares a voltage appearing in the calibration terminal ZQ with the reference voltage VMID; an impedance adjusting circuit that changes an output impedance of the replica buffer based on a result of comparison carried out by the comparing circuit; and a reference voltage adjusting circuit that adjusts the reference voltage VMID. With this arrangement, the reference voltage VMID can be offset by taking into account a resistance component present between the calibration terminal ZQ and the external terminal, and therefore, a more accurate calibration operation can be carried out.

Abstract: To provide a semiconductor memory device including: a first clock generation circuit and a second clock generation circuit that generate a first internal clock and a second internal clock, respectively; a latency counter that counts latency synchronously with the first internal clock; and a recovery counter that counts a write recovery period synchronously with the second internal clock. The second clock generation circuit activates the second internal clock when auto-precharge is designated, and deactivates the second internal clock when the auto-precharge is not designated. With this configuration, the recovery counter does not perform any counting operation when an auto-precharge function is not operated, and thus unnecessary power consumption can be prevented.

Abstract: A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle. As a result, the detection lines are charged and discharged in response to the internal clock signal of the even cycle. Consequently, the duty detection circuit can be applied to a multi-phase DLL circuit, and a potential difference appearing in the detection line can be sufficiently secured.

Abstract: A DLL circuit includes a delay line (CDL) (10) that delays a clock signal at a relatively coarse adjustment pitch, a delay line (FDL) (20) that delays the clock signal at a relatively fine adjustment pitch, and phase detecting circuits and counter control circuits that control delay amounts of the delay lines (10, 20). The counter control circuits control the delay line (10) by a linear search method, and control the delay line (20) by a binary search method. As a result, even when the number of bits of the count signal for adjusting the delay line (20) is increased, a delay amount can be determined at a high speed.

Abstract: Disclosed is a synchronous semiconductor device including clock generation circuit that frequency divides a clock signal (PCLK) input from an input buffer and generates first and second internal clock signals having a predetermined phase difference from first and second frequency-divided clock signals of different phases, respectively, a first input circuit control unit that receives a chip select signal and samples the chip select signal in synchronization with the clock signal, second and third input circuit control units that sample an output of the first input circuit control unit in synchronization with the first and second internal clock signals, respectively, and first and second input circuits that receive a result of a logic operation between the output of the first input control unit and an output of the second input circuit control unit and a result of a logic operation between the output of the first input circuit control unit and an output of the third input circuit control unit as input enable s

Abstract: A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage.

Abstract: A DLL circuit is designed to adjust the delay time and the duty applied to an input clock signal, thus producing a DLL clock signal. In a non-clocking state of the DLL clock signal in which pulses disappear temporarily, the DLL circuit stops updating the delay time and the duty of the DLL clock signal. That is, the DLL circuit is capable of preventing a phase difference between the input clock signal and the DLL clock signal from being erroneously detected in the non-clocking state of the DLL clock signal, thus preventing the delay time and the duty from being updated based on the erroneously detected phase difference. Thus, it is possible to reduce the number of cycles adapted to the delay-locked control and to thereby stabilize the operation of the DLL circuit.

Abstract: A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.

Abstract: A DLL circuit includes a delay line (CDL) (10) that delays a clock signal at a relatively coarse adjustment pitch, a delay line (FDL) (20) that delays the clock signal at a relatively fine adjustment pitch, and phase detecting circuits and counter control circuits that control delay amounts of the delay lines (10, 20). The counter control circuits control the delay line (10) by a linear search method, and control the delay line (20) by a binary search method. As a result, even when the number of bits of the count signal for adjusting the delay line (20) is increased, a delay amount can be determined at a high speed.

Abstract: A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle. As a result, the detection lines are charged and discharged in response to the internal clock signal of the even cycle. Consequently, the duty detection circuit can be applied to a multi-phase DLL circuit, and a potential difference appearing in the detection line can be sufficiently secured.

Abstract: A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. Further, the row address decoder selects the redundant word line when a replacement signal is received. A column decoder selects the bit lines in response to a column address. A row address redundancy circuit stores a redundant row address. The row address redundancy circuit provides the replacement signal when the redundant row address corresponds to the received address. The mode setting circuit receives a mode signal having a normal mode and a test mode. The mode setting circuit outputs the replacement signal to the row decoder when the mode signal is in the normal mode, and prohibits an output of the replacement signal.

Abstract: A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.

Abstract: A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. Further, the row address decoder selects the redundant word line when a replacement signal is received. A column decoder selects the bit lines in response to a column address. A row address redundancy circuit stores a redundant row address. The row address redundancy circuit provides the replacement signal when the redundant row address corresponds to the received address. The mode setting circuit receives a mode signal having a normal mode and a test mode. The mode setting circuit outputs the replacement signal to the row decoder when the mode signal is in the normal mode, and prohibits an output of the replacement signal.