Patents by Inventor Koji Miyamoto

Koji Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120063212
    Abstract: According to one embodiment, a semiconductor device includes a first transistor and a second transistor having a conductivity type which is different from a conductivity type of the first transistor, the first transistor and the second transistor being disposed on a semiconductor substrate such that a gate electrode of the first transistor and a gate electrode of the second transistor are connected to each other. The gate electrode of the first transistor includes first impurities and second impurities which suppress diffusion of the first impurities, and a concentration peak of the first impurities is formed at a shallower position than a concentration peak of the second impurities.
    Type: Application
    Filed: March 16, 2011
    Publication date: March 15, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiko Kanda, Koji Miyamoto
  • Publication number: 20110033880
    Abstract: An object of the present invention is to provide: a novel gene (polynucleotide) encoding an FAD-conjugated glucose dehydrogenase having excellent properties that it has excellent reactivity to glucose, excellent thermal stability, and excellent substrate-recognition performance and also has a low activity for maltose; a process for the production of the enzyme using a transformant cell transfected with the gene; and a method for the determination of glucose, a reagent composition for use in the determination of glucose, a biosensor for use in the determination of glucose and others, each characterized by using the enzyme obtained.
    Type: Application
    Filed: June 29, 2007
    Publication date: February 10, 2011
    Inventors: Takako Yada, Koji Miyamoto, Michinari Honda
  • Patent number: 7824665
    Abstract: The invention provides a quick-drying disinfectant gel for hands that spreads well in rubbing into hands, spreads easily over the hands, forms no scum, and is not sticky before and after drying. The disinfectant gel for hands of the invention contains 0.01 to 2.0 wt % of a maleic anhydride polymer, 0.01 to 5.0 wt % of polysaccharides, 40 to 95 wt % of a lower alcohol, and water, with the total being 100 wt %.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: November 2, 2010
    Assignee: NOF Corporation
    Inventors: Koji Miyamoto, Yoshimi Sekine, Hiroki Fukui, Kenshiro Shuto
  • Patent number: 7724047
    Abstract: A semiconductor integrated circuit includes: a switching control circuit having a first transistor and a second transistor coupled to an FET, and turning on and off the FET by turning on and off each of the first transistor and the second transistor, the FET attaining an OFF state when the first transistor is in an ON state and the second transistor is in an OFF state; a bias circuit supplying the FET with a bias voltage for turning off the FET when the first transistor and the second transistor are in an OFF state; and a protection control circuit turning off the FET by turning on the first transistor and turning off the second transistor when an abnormality is detected, and turning off the first transistor and the second transistor after a lapse of a predetermined time.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: May 25, 2010
    Assignee: Rohm Co., Ltd.
    Inventors: Eiji Nakagawa, Koji Miyamoto, Akira Aoki
  • Patent number: 7485475
    Abstract: Semiconductor elements composing a semiconductor device are formed on a semiconductor substrate. Wirings composed of copper or an alloy mainly composed of copper are formed in wiring layers through interlayer insulation films to connect the semiconductor elements to each other. When the wirings are formed, a temperature of the wirings is held in a first temperature zone covering ±40° C. of a temperature at which a stress migration is most accelerated.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: February 3, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Yoshida, Hiroshi Nakazawa, Takeshi Fujimaki, Koji Miyamoto
  • Patent number: 7432761
    Abstract: It is desirable that some voltage can be supplied as emergency backup even upon occurrence of abnormality such as a failure. The amplifier circuit in a semiconductor device supplies an output signal having a voltage produced by amplifying an input voltage Vin from a variable voltage source to one end of a coil load, and supplies a predetermined fixed voltage of 0V, for example, to the other end of the coil load to rotate the coil load with the voltage difference between these output signals, thus performing loading control of a CD tray and a DVD tray. The semiconductor device clamps the voltage of the output signal to a predetermined non-zero voltage so that a sufficient drive voltage can be obtained even if a loading control terminal T1 is grounded, thus realizing emergency backup loading control of the tray.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: October 7, 2008
    Assignee: Rohm Co., Ltd.
    Inventors: Shinsuke Takagimoto, Koji Miyamoto
  • Publication number: 20080136466
    Abstract: A semiconductor integrated circuit includes: a switching control circuit having a first transistor and a second transistor coupled to an FET, and turning on and off the FET by turning on and off each of the first transistor and the second transistor, the FET attaining an OFF state when the first transistor is in an ON state and the second transistor is in an OFF state; a bias circuit supplying the FET with a bias voltage for turning off the FET when the first transistor and the second transistor are in an OFF state; and a protection control circuit turning off the FET by turning on the first transistor and turning off the second transistor when an abnormality is detected, and turning off the first transistor and the second transistor after a lapse of a predetermined time.
    Type: Application
    Filed: December 6, 2007
    Publication date: June 12, 2008
    Applicant: ROHM CO., LTD.
    Inventors: Eiji Nakagawa, Koji Miyamoto, Akira Aoki
  • Publication number: 20080024186
    Abstract: It is desirable that some voltage can be supplied as emergency backup even upon occurrence of abnormality such as a failure. The amplifier circuit in a semiconductor device supplies an output signal having a voltage produced by amplifying an input voltage Vin from a variable voltage source to one end of a coil load, and supplies a predetermined fixed voltage of 0V, for example, to the other end of the coil load to rotate the coil load with the voltage difference between these output signals, thus performing loading control of a CD tray and a DVD tray. The semiconductor device clamps the voltage of the output signal to a predetermined non-zero voltage so that a sufficient drive voltage can be obtained even if a loading control terminal T1 is grounded, thus realizing emergency backup loading control of the tray.
    Type: Application
    Filed: June 17, 2005
    Publication date: January 31, 2008
    Inventors: Shinsuke Takagimoto, Koji Miyamoto
  • Publication number: 20070228573
    Abstract: A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.
    Type: Application
    Filed: June 13, 2007
    Publication date: October 4, 2007
    Inventors: Takeshi MATSUNAGA, Yuichi Nakashima, Koji Miyamoto
  • Patent number: 7242094
    Abstract: A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: July 10, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Matsunaga, Yuichi Nakashima, Koji Miyamoto
  • Publication number: 20070077762
    Abstract: Semiconductor elements composing a semiconductor device are formed on a semiconductor substrate. Wirings composed of copper or an alloy mainly composed of copper are formed in wiring layers through interlayer insulation films to connect the semiconductor elements to each other. When the wirings are formed, a temperature of the wirings is held in a first temperature zone covering ±40° C. of a temperature at which a stress migration is most accelerated.
    Type: Application
    Filed: November 17, 2006
    Publication date: April 5, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenji YOSHIDA, Hiroshi Nakazawa, Takeshi Fujimaki, Koji Miyamoto
  • Publication number: 20070065388
    Abstract: The invention provides a quick-drying disinfectant gel for hands that spreads well in rubbing into hands, spreads easily over the hands, forms no scum, and is not sticky before and after drying. The disinfectant gel for hands of the invention contains 0.01 to 2.0 wt % of a maleic anhydride polymer, 0.01 to 5.0 wt % of polysaccharides, 40 to 95 wt % of a lower alcohol, and water, with the total being 100 wt %.
    Type: Application
    Filed: September 20, 2006
    Publication date: March 22, 2007
    Inventors: Koji Miyamoto, Yoshimi Sekine, Hiroki Fukui, Kenshiro Shuto
  • Patent number: 7157368
    Abstract: Semiconductor elements composing a semiconductor device are formed on a semiconductor substrate. Wirings composed of copper or an alloy mainly composed of copper are formed in wiring layers through interlayer insulation films to connect the semiconductor elements to each other. When the wirings are formed, a temperature of the wirings is held in a first temperature zone covering ±40° C. of a temperature at which a stress migration is most accelerated.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: January 2, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Yoshida, Hiroshi Nakazawa, Takeshi Fujimaki, Koji Miyamoto
  • Patent number: 6960492
    Abstract: There is provided a method of manufacturing a semiconductor device having a number of wiring layers, comprising forming an underlayer, the underlayer including a substrate, at least one underlayer wiring layer provided on the substrate, and a first attachment surface, forming at least one upper structure, the upper structure including at least one upper wiring layer and a second attachment surface, and positioning the upper structure and the underlayer and attaching the first and second attachment surfaces to each other.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: November 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koji Miyamoto
  • Publication number: 20040245645
    Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.
    Type: Application
    Filed: June 22, 2004
    Publication date: December 9, 2004
    Inventors: Koji Miyamoto, Kenji Yoshida, Hisashi Kaneko
  • Publication number: 20040207043
    Abstract: A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.
    Type: Application
    Filed: July 25, 2003
    Publication date: October 21, 2004
    Inventors: Takeshi Matsunaga, Yuichi Nakashima, Koji Miyamoto
  • Patent number: 6774024
    Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: August 10, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Miyamoto, Kenji Yoshida, Hisashi Kaneko
  • Publication number: 20040104482
    Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.
    Type: Application
    Filed: November 21, 2003
    Publication date: June 3, 2004
    Inventors: Koji Miyamoto, Kenji Yoshida, Hisashi Kaneko
  • Publication number: 20040106219
    Abstract: Semiconductor elements composing a semiconductor device are formed on a semiconductor substrate. Wirings composed of copper or an alloy mainly composed of copper are formed in wiring layers through interlayer insulation films to connect the semiconductor elements to each other. When the wirings are formed, a temperature of the wirings is held in a first temperature zone covering 40° C. of a temperature at which a stress migration is most accelerated.
    Type: Application
    Filed: August 18, 2003
    Publication date: June 3, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenji Yoshida, Hiroshi Nakazawa, Takeshi Fujimaki, Koji Miyamoto
  • Patent number: D595192
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: June 30, 2009
    Assignee: Mazda Motor Corporation
    Inventors: Kunihiko Kurisu, Akira Tamatani, Kosuke Takahashi, Koji Miyamoto, Masatoshi Miyake, Ryuji Kumagai, Keisuke Nakai, Tomoyuki Suzuki