Abstract: An SRAM includes: first and second access PMOS transistors formed on an N well region; first and second driver NMOS transistors formed on a P well region; a word line; and first and second bit lines. Active regions are extended in the same direction, polysilicon wirings for forming gates of each of the MOS transistors are extended in the same direction, and drains of the first and second access PMOS transistors are connected to drains of the first and second driver NMOS transistors using first metal wirings without interposing the polysilicon wirings forming the gates of the first and second driver NMOS transistors therebetween, respectively.

Abstract: The semiconductor memory device includes two PMOS transistors that make the SRAM memory cell. The gate insulating films of these PMOS transistors are formed using a material that has a high permittivity. As a result, the capacitance of memory nodes is increased, and the probability of soft errors is lowered.

Abstract: The dummy cell of the SRAM corresponds to a normal memory cell of which first and second P-channel MOS transistors for loading are replaced by the first and the second N-channel MOS transistors, of which gate and source are provided with power supply potential and ground potential, respectively. When a word line rises to “H” level, third and fourth N-channel MOS transistors for accessing are rendered conductive, to pass current from dummy bit line to a line of ground potential via the third N-channel MOS transistor, the first N-channel MOS transistor, and a fifth N-channel MOS transistor for driving. Accordingly, speed of potential decrease of the dummy bit line may be faster than that of bit line. Hence, operational timing can easily be optimized, and operational margin can be increased.

Abstract: Dummy cells each having the same layout as a normal memory cell are aligned in a row direction to the normal memory cells, and are arranged in rows and columns. In each dummy cell column, a dummy bit line is arranged, and a plurality of dummy cells are simultaneously selected and connected to the corresponding dummy bit line when one word line is selected. A voltage detecting circuit detects the potentials on the dummy bit lines to determine timing of activation of a sense amplifier. In the semiconductor memory device, the potential on the dummy bit line can be changed at high speed, and internal data read timing can be optimized independent of a structure of a memory cell array.

Abstract: A memory device that consumes no wasteful power in selecting memory cells and achieves high operating speed and size and cost reductions, is provided. In reading of memory cell information, only a single memory cell in a single local block is activated through a read word line. Specifically, AND circuits are provided in correspondence with all memory cells. Each AND circuit receives as its inputs a block select signal for selecting one of the local blocks and an in-block memory cell select signal for selecting one of the memory cells in each local block in a common manner among the local blocks. The outputs from the AND circuits are applied to read word lines. Unselected memory cells are not activated and therefore no current flows from those memory cells to local read bit lines, thereby preventing wasteful power consumption.

Abstract: A method of manufacturing a semiconductor device which is capable of forming a gate structure having dimensions as designed. A silicon oxide film, a polysilicon film and a silicon oxide film are formed in the order named on a silicon substrate. Then, the silicon oxide film is patterned to form silicon oxide films. Next, a photoresist is applied, and is then exposed to light using a photomask for defining the ends of gate structures as seen in a direction of a gate width. Next, the photoresist is developed to form openings. Using the photoresist as an etch mask, portions of the silicon oxide films exposed in the openings are etched away.

Abstract: Dummy cells are divided into a plurality of divided dummy columns, and divided dummy bit lines are arranged corresponding to the divided dummy columns. These divided dummy bit lines are provided with dummy sense amplifiers that drive a sense control line transmitting a sense enable signal activating a sense amplifier. A faster activation timing of the sense amplifier can be achieved.

Abstract: An SRAM includes a plurality of memory cells which are arranged in an extension direction of bit lines, each of which has a long edge and a short edge, an extension direction of the short edge being equal to the extension direction of the bit lines. A distance between polysilicon wirings which are formed in one of the memory cells and which become gates of NMOS transistors arranged in the extension direction of the bit lines, respectively, differs from a distance between the polysilicon wiring and the polysilicon wiring which becomes a gate of an NMOS transistor formed in the other memory cell.

Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.

Abstract: Dummy cells each having the same layout as a normal memory cell are aligned in a row direction to the normal memory cells, and are arranged in rows and columns. In each dummy cell column, a dummy bit line is arranged, and a plurality of dummy cells are simultaneously selected and connected to the corresponding dummy bit line when one word line is selected. A voltage detecting circuit detects the potentials on the dummy bit lines to determine timing of activation of a sense amplifier. In the semiconductor memory device, the potential on the dummy bit line can be changed at high speed, and internal data read timing can be optimized independent of a structure of a memory cell array.

Abstract: In a multiport SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in the same direction. With the configuration, a semiconductor memory device having a low-power consumption type SRAM memory cell with an increased margin of variations in manufacturing, by which a bit line can be shortened in a multiport SRAM memory cell or an associative memory, can be obtained.

Abstract: An SRAM memory cell includes two inverters connected in complement with each other. Each inverter includes one NMOS transistor and one PMOS transistor. The gate of the NMOS transistor in one inverter is connected to the drain of the NMOS transistor in the other inverter and this forms a first node. The drain of the NMOS transistor in one inverter is connected to the gate of the NMOS transistor in the other inverter and this forms a second node. The drain of an another PMOS transistor and the gate of still another PMOS transistor are connected to the first node. The drain of the still another PMOS transistor and the gate of the another PMOS transistor are connected to the second node. The gate capacitance and drain capacitance of these PMOS transistors is appended to the two nodes.

Abstract: In a semiconductor memory device of the present invention, four access transistors of two memory cells arranged adjacent to each other in the same row are formed within a common p-type well, and each gate of access transistors of memory cell and each gate of access transistors and of memory cell are electrically connected to different word lines. Thereby, it is possible to obtain a semiconductor memory device capable of reducing generation of multi-bit errors.

Abstract: A semiconductor storage apparatus having an SRAM memory cell of a low power consumption type which can reduce a wiring length of a bit line. NMOS transistors (N1), (N3) and (N4) are formed in a P well region (PW0), NMOS transistors (N2), (N5) and (N6) are formed in a P well region (PW1), and a wiring direction (a second direction) of bit lines (BL1) and (BL2) (bit lines BL12 and BL22) is set to be orthogonal to a direction of separation arrangement (a transverse direction in the drawing; a first direction) of the P well regions (PW0) and (PW1). The P well region (PW0) and the P well region (PW1) are formed opposite to each other with an N well region (NW) interposed therebetween.

Abstract: Provided is a semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.

Abstract: A memory cell of SRAM includes: two N-channel MOS transistors connected in series between a first storage node and a line of a ground potential and two N-channel MOS transistors connected in series between a second storage node and a line of a ground potential. Since no storage data is inverted unless one &agr;-particle passes through two N-channel MOS transistors, a soft error hard to occur.

Abstract: A semiconductor memory device is provided with: first and second access PMOS transistors formed on N well regions; first and second driver NMOS transistors formed on a P well region; a word line connected to the gates of first and second access PMOS transistors; and first and second bit lines connected to the sources of first and second access PMOS transistors, respectively. Then, N-type diffusion regions and P-type diffusion regions extend in the same direction while polysilicon interconnections extend in the same direction.

Abstract: This invention is a semiconductor storage apparatus having an SRAM memory cell of a low power consumption type which can reduce a wiring length of a bit line. NMOS transistors (N1), (N3) and (N4) are formed in a P well region (PW0), NMOS transistors (N2), (N5) and (N6) are formed in a P well region (PW1), and a wiring direction (a second direction) of bit lines (BL1) and (BL2) (bit lines BL12 and BL22) is set to be orthogonal to a direction of separation arrangement (a transverse direction in the drawing; a first direction) of the P well regions (PW0) and (PW1). The P well region (PW0) and the P well region (PW1) are formed opposite to each other with an N well region (NW) interposed therebetween.

Abstract: An SRAM memory cell is constituted by complementarily connecting first inverter composed of NMOS transistor and a PMOS transistor, and a second inverter composed of another NMOS transistor and another PMOS transistor. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the first inverter. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the second inverter. As a result, capacity values for gate capacities are added to the storage nodes.

Abstract: In the construction of a P-well area including a pair of CMOS inverters and a N-well area of a multi-port SRAM cell, the P-well area is divided into two P-well areas. These two P-well areas are disposed on two sides of the N-well area. A layout is provided such that the boundaries between the P-well areas and the N-well area are parallel to bit lines. Two access gates are located in one P-well area and two access gates are located in the other P-well area. Thus, the bit lines can be made shorter, and the amount of wiring can be reduced.