Abstract: When to a memory cell array 21 a read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into memory units 31 to 37 each of which has four bits which are arranged along a direction of a word line. On writing the 7-bit data in the memory cell array, bits of the 7-bit data that are different from one another are written as written bit data along the direction of the word line in the memory units 31 to 37, respectively. In the 7-bit data, the written bit data has an interval off our bits. Error correcting circuits performs an error correction of the 7-bit data in each of the 7-bit data.

Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter includes a NMOS transistor and a PMOS transistor, and an inverter includes a NMOS transistor and a PMOS transistor. The inverters are subjected to cross section. The NMOS transistor is formed within a P well region, and NMOS transistor is formed within a P well region. The P well regions are oppositely disposed with an N well region interposed therebetween.

Abstract: With a P well region being divided, NMOS transistors N1 and N3 are formed in the first P well region, and NMOS transistors N2 and N4 in the second P well region. Alternatively, with a N well region being divided, PMOS transistor P1 is formed in the first N well region, and PMOS transistor P2 in the second N well region.

Abstract: N well contact area 13 is integrally formed with second diffused area 12 within the upper parts of a N well and a P well, and P well contact area 14 is integrally formed with first diffused area 11 in the upper parts of the P well and the N well.

Abstract: A semiconductor memory includes a first inverter, a second inverter and a read circuit. The first inverter has its input terminal connected to a first memory node and its output terminal connected to a second memory node. The second inverter is connected in anti-parallel with the first inverter, that is, has its input terminal connected to the second memory node and its output terminal connected to the first memory node. The read circuit includes a first transistor having its gate connected to the first memory node, a second transistor having its gate connected to the second memory node, and a third transistor for connecting the drain of the first transistor and that of the second transistor to a read bit line. The semiconductor memory can improve its soft error resistance without increasing the number of steps of the manufacturing process.

Abstract: A semiconductor memory includes a first inverter, a second inverter and a read circuit. The first inverter has its input terminal connected to a first memory node and its output terminal connected to a second memory node. The second inverter is connected in anti-parallel with the first inverter, that is, has its input terminal connected to the second memory node and its output terminal connected to the first memory node. The read circuit includes a first transistor having its gate connected to the first memory node, a second transistor having its gate connected to the second memory node, and a third transistor for connecting the drain of the first transistor and that of the second transistor to a read bit line. The semiconductor memory can improve its soft error resistance without increasing the number of steps of the manufacturing process.

Abstract: A method of manufacturing a semiconductor device which is capable of forming a gate structure having dimensions as designed is provided. A silicon oxide film (4), a polysilicon film (5) and a silicon oxide film (6) are formed in the order named on a silicon substrate (1). Then, the silicon oxide film (6) is patterned to form silicon oxide films (14a, 14b). Next, a photoresist (15) is applied, and is then exposed to light using a photomask (18) for defining the ends of gate structures (25i-25k) as seen in a direction of a gate width. Next, the photoresist (15) is developed to form openings (21s-21u). Using the photoresist (15) as an etch mask, portions of the silicon oxide films (14a, 14b) exposed in the openings (21s-21u) are etched away.

Abstract: A gate of an NMOS transistor (N1) is connected to a memory terminal (Na) and a gate of an NMOS transistor (N2) is connected to a memory terminal (Nb). Sources of the NMOS transistors (N1, N2) are commonly connected to an internal terminal (Nc) and a ground potential (GND). Potentials of backgate terminals (BN1, BN2) of the NMOS transistors (N1, N2) are set to the ground potential (GND). When PMOS transistors (P1, P2) are in ON and OFF states, respectively, the memory terminal (Na) is brought into a logical “H” state and the memory terminal (Nb) remains a logical “L” state by a gate-leak current passing from the gate of the NMOS transistor (N2) to a semiconductor substrate. With such a structure, a semiconductor memory device having a memory cell structure to ensure reduction in cell area can be achieved.

Abstract: The semiconductor memory device comprises two PMOS transistors that make the SRAM memory cell. The gate insulating films of these PMOS transistors are formed using a material that has a high permittivity. As a result, the capacitance of memory nodes is increased, and the probability of soft errors is lowered.

Abstract: A gate of an NMOS transistor (N1) is connected to a memory terminal (Na) and a gate of an NMOS transistor (N2) is connected to a memory terminal (Nb). Sources of the NMOS transistors (N1, N2) are commonly connected to an internal terminal (Nc) and a ground potential (GND). Potentials of backgate terminals (BN1, BN2) of the NMOS transistors (N1, N2) are set to the ground potential (GND). When PMOS transistors (P1, P2) are in ON and OFF states, respectively, the memory terminal (Na) is brought into a logical “H” state and the memory terminal (Nb) remains a logical “L” state by a gate-leak current passing from the gate of the NMOS transistor (N2) to a semiconductor substrate. With such a structure, a semiconductor memory device having a memory cell structure to ensure reduction in cell area can be achieved.

Abstract: In the semiconductor storage device, a dummy P+ diffusion region which does not contribute to a storage operation is formed in the vicinity of two P+ diffusion regions constituting a storage node. Moreover, a dummy N+ diffusion region which does not contribute to the storage operation is formed in the vicinity of N+ diffusion regions FL210 and FL220 constituting a storage node. Consequently, a part of electrons generated in a P well region PW by irradiation of &agr; rays or neutron rays can be collected into the dummy N+ diffusion region FL250, and a part of holes generated in an N well region NW by the irradiation of the &agr; rays or the neutron rays can be collected into the dummy P+ diffusion region FL150.

Abstract: There is provided a semiconductor device including a transistor formed by means of a common contact hole that connects a gate electrode, and a diffused layer forming a source/drain terminal; and a semiconductor device comprising the gate electrode of the transistor, and a connecting terminal to which capacitance between substrates and capacitance between the gate electrode and the source/drain terminal are added, thereby improving the soft error resistance caused by alpha rays and neutron beams.

Abstract: Provided is a semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.

Abstract: In the construction of a P-well area formed with a pair of CMOS inverters and a N-well area that constitute a multi-port SRAM cell, the P-well area is divided into two P-well areas. These two P-well areas are disposed on the two sides of the N-well area. A layout is provided such that the boundaries between the P-well areas and the N-well area are parallel to the bit lines. Two access gates are formed in one P-well area and two access gates are formed in the other P-well area. Thus, the bit lines can be made shorter, and the amount of wiring can be reduced.

Abstract: The SRAM memory cell comprises two inverters connected in complement with each other. Each inverter comprises one NMOS transistor and one PMOS transistor. Gate of the NMOS transistor in one inverter is connected to the drain of the NMOS transistor in the other inverter and this forms a first node. Drain of the NMOS transistor in one inverter is connected to the gate of the NMOS transistor in the other inverter and this forms a second node. Drain of an another PMOS transistor and gate of still another PMOS transistor are connected to the first node. Drain of the still another PMOS transistor and the gate of the another PMOS transistor are connected to the second node. The gate capacity and drain capacity of these PMOS transistors is appended to the two nodes.

Abstract: In the construction of a P-well area including a pair of CMOS inverters and a N-well area of a multi-port SRAM cell, the P-well area is divided into two P-well areas. These two P-well areas are disposed on two sides of the N-well area. A layout is provided such that the boundaries between the P-well areas and the N-well area are parallel to bit lines. Two access gates are located in one P-well area and two access gates are located in the other P-well area. Thus, the bit lines can be made shorter, and the amount of wiring can be reduced.

Abstract: An SRAM memory cell is constituted by complementarily connecting first inverter composed of NMOS transistor and a PMOS transistor, and a second inverter composed of another NMOS transistor and another PMOS transistor. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the first inverter. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the second inverter. As a result, capacity values for gate capacities are added to the storage nodes.

Abstract: In the construction of a P-well area formed with a pair of CMOS inverters and a N-well area that constitute a multi-port SRAM cell, the P-well area is divided into two P-well areas. These two P-well areas are disposed on the two sides of the N-well area. A layout is provided such that the boundaries between the P-well areas and the N-well area are parallel to the bit lines. Two access gates are formed in one P-well area and two access gates are formed in the other P-well area. Thus, the bit lines can be made shorter, and the amount of wiring can be reduced.

Abstract: Provided is a semiconductor integrated circuit capable of reducing power consumption in an electric potential converting circuit for converting an electric potential of a bit line. The semiconductor integrated circuit according to the present invention comprises bit lines BL1 and BL2, a precharge circuit PCC which is connected to the bit lines BL1 and BL2, an electric potential converting circuit SA, and a memory cell MC. The electric potential converting circuit SA has a current path for transistors T3, T4 and T6 and a current path for the transistor T3 and transistors T5 and T9 provided between a high potential V2 and a ground potential GND. Respective gate electrodes of the transistors T3, T4, T6 and T9 receive a mode signal PC, and respective gate electrodes of the transistors T4 and T5 are connected to the bit lines BL1 and BL2.

Abstract: A layout pattern of a memory cell circuit has a plurality of basic cells. Each basic cell has a small aspect ratio. Each basic cell has a NMOS transistor and a PMOS transistor. In the layout pattern, one basic cell is arranged in each row direction and the sixteen basic cells are arranged in each column direction.