Patents by Inventor Koji Obata

Koji Obata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240140918
    Abstract: A compound represented by formula (1) below, useful for treating cancer. In the formula, R1 and R3-R8 each independently represents a hydrogen atom or an alkyl group, R2 represents a hydrogen atom or a group represented by —ORa, R9 represents a group represented by —C(O)NRcRf, Ra, Re, and Rf each independently represents a hydrogen atom, an arylalkyl group that may have a substituent, or a heteroarylalkyl group.
    Type: Application
    Filed: January 28, 2022
    Publication date: May 2, 2024
    Inventors: Isamu SHIINA, Motoyuki SHIMONAKA, Takatsugu MURATA, Yuuki OBATA, Toshirou NISHIDA, Koji OKAMOTO
  • Patent number: 11916563
    Abstract: Provided are an analog-to-digital (AD) converter, a sensor processing circuit, and a sensor system capable of improving responsiveness of feedback control. AD converter includes input part, AD conversion part, first output part, and second output part. The analog signal output from sensor is input to input part. AD conversion part digitally converts an analog signal to generate first digital data and second digital data. First output part outputs the first digital data to control circuit. Second output part outputs the second digital data to sensor before first output part outputs the first digital data.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: February 27, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Jun'Ichi Naka, Koji Obata, Junji Nakatsuka, Hiroki Yoshino, Masaaki Nagai
  • Publication number: 20240038726
    Abstract: An AI module includes a first semiconductor chip. The first semiconductor chip includes a plurality of operation blocks each of which performs a predetermined operation and a plurality of memory blocks each including memory. The plurality of operation blocks and the plurality of memory blocks are arranged in a checkered pattern or in a striped pattern in plan view.
    Type: Application
    Filed: December 21, 2021
    Publication date: February 1, 2024
    Inventors: Koji OBATA, Masaru SASAGO, Masamichi NAKAGAWA, Tatsuya KABE, Hiroyuki GOMYO, Masatomo MITSUHASHI, Yutaka SONODA
  • Publication number: 20230370083
    Abstract: A comparator compares a differential voltage between a voltage to be converted as an analog input voltage and a comparative voltage generated by a D/A converting unit with a comparison reference voltage. A switching circuit selectively connects a capacitor, associated with the analog input voltage selected as the voltage to be converted, to an output terminal of an integrator. The integrator integrates the differential voltage in a state where an A/D converting section has performed conversion operation on a least significant bit. A comparison reference voltage generating unit uses, as the comparison reference voltage, a charge voltage for the capacitor associated with the analog input voltage selected as the voltage to be converted.
    Type: Application
    Filed: June 15, 2021
    Publication date: November 16, 2023
    Inventor: Koji OBATA
  • Publication number: 20230344442
    Abstract: A D/A converting unit generates a comparative voltage corresponding to a target bit falling within a range from a most significant bit through a least significant bit. A comparator determines a value of the target bit by comparing a differential voltage between an output signal of an input switching unit and a comparative voltage generated by the D/A converting unit with a reference voltage. An integrator integrates a conversion error. In a first conversion operation of converting a first signal, a control unit sets, based on a result obtained by the integrator, the reference voltage for use when the first signal to be provided next time as the output signal by the input switching unit is A/D converted. In a second conversion operation of A/D converting a second signal, the control unit sets the reference voltage at a constant voltage level.
    Type: Application
    Filed: June 10, 2021
    Publication date: October 26, 2023
    Inventors: Jun'ichi NAKA, Koji OBATA
  • Publication number: 20230197711
    Abstract: An artificial intelligence (AI) chip includes: a plurality of memory dies each for storing data; a plurality of computing dies each of which performs a computation included in an AI process; and a system chip that controls the plurality of memory dies and the plurality of computing dies. Each of the plurality of memory dies has a first layout pattern. Each of the plurality of computing dies has a second layout pattern. A second memory die which is one of the plurality of memory dies is stacked above the first layout pattern of a first memory die which is one of the plurality of memory dies. A second computing die which is one of the plurality of computing dies is stacked above the second layout pattern of a first computing die which is one of the plurality of computing dies.
    Type: Application
    Filed: April 14, 2021
    Publication date: June 22, 2023
    Inventors: Shoichi GOTO, Koji OBATA, Masaru SASAGO, Masamichi NAKAGAWA
  • Patent number: 11677411
    Abstract: An A/D converter includes an A/D conversion unit and an output unit. The A/D conversion unit includes a second A/D converter (successive approximation register A/D converter) and generates first digital data having a first number of bits and second digital data having a second number of bits, where the second number of bits is smaller than the first number of bits. The output unit provides first output information that is the first digital data and also provides second output information based on the second digital data. The output unit provides the second output information before providing the first output information.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 13, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Junji Nakatsuka, Hiroki Yoshino, Jun'ichi Naka, Koji Obata, Masaaki Nagai
  • Patent number: 11664815
    Abstract: A digital filter is used in an A/D converter and includes a first filter and second filter. The first filter outputs first digital data by performing filter processing on output of an A/D conversion unit included in the A/D converter. The second filter outputs second digital data by performing filter processing on the output of the A/D conversion unit. The second digital data has either a lower resolution or a smaller effective number of bits than the first digital data does. The second filter outputs the second digital data before the first filter outputs the first digital data.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: May 30, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masaaki Nagai, Hiroki Yoshino, Junji Nakatsuka, Jun'ichi Naka, Koji Obata
  • Publication number: 20230122673
    Abstract: A data generation method includes a first acquisition step, a second acquisition step, and a generation step. The first acquisition step includes acquiring result information about a result of a classification executed by a living being on a target. The second acquisition step includes acquiring execution information about execution of the classification. The generation step includes generating data for machine learning based on the result information and the execution information. The data for machine learning includes learning data and evaluation information about evaluation of the learning data.
    Type: Application
    Filed: March 9, 2021
    Publication date: April 20, 2023
    Inventors: Junko ONOZAKI, Koji OBATA, Hisashi AIKAWA, Yuya SUGASAWA
  • Patent number: 11611349
    Abstract: Provided are an analog-to-digital (AD) converter, a sensor system, and a test system capable of reducing the time for test processing. AD converter includes input part, AD conversion part, first output part, and second output part. The analog signal output from sensor is input to input part. AD conversion part digitally converts an analog signal to generate first digital data and second digital data. First output part outputs the first digital data to control circuit. Second output part outputs the second digital data to test controller before first output part outputs the first digital data. In the test mode, test controller determines whether or not sensor system including sensor is in an abnormal state on the basis of the second digital data.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: March 21, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Koji Obata, Jun'ichi Naka, Junji Nakatsuka, Hiroki Yoshino, Masaaki Nagai
  • Publication number: 20220173746
    Abstract: An A/D converter includes an A/D conversion unit and an output unit. The A/D conversion unit includes a second A/D converter (successive approximation register A/D converter) and generates first digital data having a first number of bits and second digital data having a second number of bits, where the second number of bits is smaller than the first number of bits. The output unit provides first output information that is the first digital data and also provides second output information based on the second digital data. The output unit provides the second output information before providing the first output information.
    Type: Application
    Filed: February 28, 2020
    Publication date: June 2, 2022
    Inventors: Junji NAKATSUKA, Hiroki YOSHINO, Jun'ichi NAKA, Koji OBATA, Masaaki NAGAI
  • Publication number: 20220158652
    Abstract: A digital filter is used in an A/D converter and includes a first filter and second filter. The first filter outputs first digital data by performing filter processing on output of an A/D conversion unit included in the A/D converter. The second filter outputs second digital data by performing filter processing on the output of the A/D conversion unit. The second digital data has either a lower resolution or a smaller effective number of bits than the first digital data does. The second filter outputs the second digital data before the first filter outputs the first digital data.
    Type: Application
    Filed: February 28, 2020
    Publication date: May 19, 2022
    Inventors: Masaaki NAGAI, Hiroki YOSHINO, Junji NAKATSUKA, Jun'ichi NAKA, Koji OBATA
  • Publication number: 20220123757
    Abstract: Provided are an analog-to-digital (AD) converter, a sensor processing circuit, and a sensor system capable of improving responsiveness of feedback control. AD converter includes input part, AD conversion part, first output part, and second output part. The analog signal output from sensor is input to input part. AD conversion part digitally converts an analog signal to generate first digital data and second digital data. First output part outputs the first digital data to control circuit. Second output part outputs the second digital data to sensor before first output part outputs the first digital data.
    Type: Application
    Filed: March 9, 2020
    Publication date: April 21, 2022
    Inventors: JUN'ICHI NAKA, KOJI OBATA, JUNJI NAKATSUKA, HIROKI YOSHINO, MASAAKI NAGAI
  • Publication number: 20220123758
    Abstract: Provided are an analog-to-digital (AD) converter, a sensor system, and a test system capable of reducing the time for test processing. AD converter includes input part, AD conversion part, first output part, and second output part. The analog signal output from sensor is input to input part. AD conversion part digitally converts an analog signal to generate first digital data and second digital data. First output part outputs the first digital data to control circuit. Second output part outputs the second digital data to test controller before first output part outputs the first digital data. In the test mode, test controller determines whether or not sensor system including sensor is in an abnormal state on the basis of the second digital data.
    Type: Application
    Filed: March 13, 2020
    Publication date: April 21, 2022
    Inventors: KOJI OBATA, JUN'ICHI NAKA, JUNJI NAKATSUKA, HIROKI YOSHINO, MASAAKI NAGAI
  • Publication number: 20210249109
    Abstract: An information processing system includes an acquisition unit configured to acquire a first surgical record that is a record of information regarding an operation of a medical device used in surgery, a conversion unit (101) configured to perform protection processing for personal information of a patient included in the first surgical record to convert the first surgical record into a second surgical record, an identification information generation unit (102) configured to generate first identification information associated with the first surgical record and second identification information associated with the second surgical record, and a determination unit (103) configured to determine which of the first surgical record associated with the first identification information and the second surgical record associated with the second identification information is to be transmitted to a node (30) used by the user on the basis of authority information regarding an authority of the user.
    Type: Application
    Filed: June 18, 2019
    Publication date: August 12, 2021
    Applicant: Sony Corporation
    Inventors: Shunsuke HAYASHI, Hideto SHIKATA, Hiroo MIURA, Akihiko NAKATANI, Koji OBATA
  • Patent number: 11033176
    Abstract: The present disclosure relates to a surgical system, a surgical device, and a surgical method with which startup time can be shortened. Upon receipt of an instruction from a startup execution process, a high-speed startup driver creates a high-speed startup image and writes it to an SSD. The startup execution process is a process that is executed first after an OS is started up, and has the function of executing, in cooperation with the high-speed startup driver, startup of various processes in an endoscope program, creation of a high-speed startup image, and return from the high-speed startup image. The present disclosure can be applied to, for example, a surgical system provided with an imaging device including an endoscope or a microscope.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: June 15, 2021
    Assignee: SONY CORPORATION
    Inventors: Koji Obata, Makoto Korehisa, Kazumi Sato, Kan Iibuchi, Kazunori Yamamoto
  • Publication number: 20200372317
    Abstract: A wireless communication semiconductor device includes a circuit board, a semiconductor chip mounted on the circuit board, a thin film transistor provided on the circuit board, and an antenna provided on the circuit board. Even if a different unique ID is assigned to each of the wireless communication semiconductor devices, as compared with silicon-based wireless communication semiconductor devices, a manufacturing cost per device is sufficiently reduced, and the reduction in operation speed and reliability is sufficiently prevented.
    Type: Application
    Filed: January 23, 2019
    Publication date: November 26, 2020
    Inventors: KOJI OBATA, HIDEYUKI ARAI, JUN'ICHI NAKA
  • Publication number: 20200342282
    Abstract: Improving safety against peeling-off of a semiconductor device from an article and omitting an adhesion work of the semiconductor device to the article are made possible. Provided is semiconductor device including one or more components selected from a group including semiconductor chip, thin film transistor, antenna, and wiring. The one or more components are directly fixed on a surface of article. Provided is a manufacturing method of semiconductor device including one or more components selected from a group including semiconductor chip, thin film transistor, antenna, and wiring. The manufacturing method includes at least one of following step P1 and step Q1: step P1 of directly mounting the semiconductor chip on a surface of an article; and step Q1 of directly forming one or more components selected from a group including the thin film transistor, the antenna, and the wiring on the surface of the article by a printing method.
    Type: Application
    Filed: February 4, 2019
    Publication date: October 29, 2020
    Inventors: KOJI OBATA, HIDEYUKI ARAI, JUN'ICHI NAKA
  • Publication number: 20200280269
    Abstract: The present disclosure provides a vibration power generation device capable of generating large electric power relative to an amount of displacement of a portion of a specimen. Vibration power generation device according to the present invention includes piezoelectric part and displacement enhancer. In response to displacement of a portion of specimen, displacement enhancer displaces a portion of piezoelectric part by a displacement amount greater than an amount of the displacement of the portion of specimen. When the portion of piezoelectric part is displaced, piezoelectric part generates electric power in accordance with an amount of the displacement of the portion of piezoelectric part.
    Type: Application
    Filed: October 26, 2018
    Publication date: September 3, 2020
    Inventors: HIDEYUKI ARAI, JUN'ICHI NAKA, TOSHIAKI OZEKI, KOJI OBATA
  • Patent number: 10340868
    Abstract: An amplifier circuit includes a first input branch circuit including a first sampling capacitor, a second input branch circuit including a second sampling capacitor, an averaging capacitor, and a subtraction capacitor, a feedback capacitor, and an operational amplifier. The first sampling capacitor samples an input voltage in a first time period and outputs a first voltage. The second sampling capacitor samples the input voltage in the first time period and outputs a second voltage. The averaging capacitor takes an average of the second voltage in the second time period and outputs a third voltage. The subtraction capacitor receives the third voltage in the first time period. The subtraction capacitor subtracts the first voltage from the third voltage and outputs a fourth voltage in the second time period. The operational amplifier is connected to the feedback capacitor and amplifies the fourth voltage. The first and second time periods are repeated alternately.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 2, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Koji Obata, Kazuo Matsukawa