Patents by Inventor Koji Taya

Koji Taya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7834470
    Abstract: The present invention include a semiconductor device and a method therefore, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefore, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: November 16, 2010
    Assignee: Spansion LLC
    Inventors: Koji Taya, Masanori Onodera, Junji Tanaka, Kouichi Meguro
  • Publication number: 20100276801
    Abstract: A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.
    Type: Application
    Filed: July 15, 2010
    Publication date: November 4, 2010
    Inventors: Masataka Hoshino, Ryoto Fukuyama, Koji Taya
  • Patent number: 7786587
    Abstract: A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: August 31, 2010
    Assignee: Spansion LLC
    Inventors: Masataka Hoshino, Ryoto Fukuyama, Koji Taya
  • Patent number: 7696616
    Abstract: A stacked type semiconductor device includes semiconductor devices, interposers by which the semiconductor devices are stacked, the interposers having electrodes provided on sides thereof, and a connection substrate connecting the electrodes together. The electrodes provided on the sides of the interposers may be connected to the connection substrate by one of an electrically conductive adhesive or an anisotropically conductive film.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: April 13, 2010
    Assignee: Spansion LLC
    Inventors: Yasuhiro Shinma, Masanori Onodera, Kouichi Meguro, Koji Taya, Junji Tanaka, Junichi Kasai
  • Patent number: 7642637
    Abstract: A carrier for a stacked type semiconductor device includes a lower carrier having a first accommodating portion that accommodates a first semiconductor device, and an upper carrier having a second accommodating portion that accommodates a second semiconductor device stacked on the first semiconductor device so as to be placed in position on the first semiconductor device. It is thus possible to eliminate an additional device used for stacking the semiconductor device, and thereby reduce the cost.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: January 5, 2010
    Assignee: Spansion LLC
    Inventors: Masanori Onodera, Junichi Kasai, Kouichi Meguro, Junji Tanaka, Yasuhiro Shinma, Koji Taya
  • Publication number: 20090325346
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Application
    Filed: September 9, 2009
    Publication date: December 31, 2009
    Inventors: Masataka HOSHINO, Junichi KASAI, Kouichi MEGURO, Ryota FUKUYAMA, Yasuhiro SHINMA, Koji TAYA, Masanori ONODERA, Naomi MASUDA
  • Publication number: 20090321958
    Abstract: Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor chip, an insulating member for electrically insulating the semiconductor chip from the connector terminal, and a first connection member for electrically coupling the semiconductor chip with the connector terminal. Simplified step of manufacturing the connector terminal may further simplify the steps of manufacturing the semiconductor device.
    Type: Application
    Filed: December 22, 2008
    Publication date: December 31, 2009
    Inventors: Junji TANAKA, Koji TAYA, Masahiko HARAYAMA
  • Patent number: 7605457
    Abstract: The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: October 20, 2009
    Assignee: Spansion LLC
    Inventors: Masataka Hoshino, Junichi Kasai, Kouichi Meguro, Ryota Fukuyama, Yasuhiro Shinma, Koji Taya, Masanori Onodera, Naomi Masuda
  • Publication number: 20090256250
    Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.
    Type: Application
    Filed: June 24, 2009
    Publication date: October 15, 2009
    Inventors: Koji TAYA, Masanori ONODERA, Junji TANAKA, Kouichi MEGURO
  • Publication number: 20090200684
    Abstract: The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of the excess underfill by providing a shelf in the semiconductor chip.
    Type: Application
    Filed: December 23, 2008
    Publication date: August 13, 2009
    Inventors: Naomi MASUDA, Koji TAYA
  • Patent number: 7566978
    Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: July 28, 2009
    Assignee: Spansion LLC
    Inventors: Koji Taya, Masanori Onodera, Junji Tanaka, Kouichi Meguro
  • Publication number: 20090174057
    Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.
    Type: Application
    Filed: March 13, 2009
    Publication date: July 9, 2009
    Inventors: Koji TAYA, Masanori ONODERA, Junji TANAKA, Kouichi MEGURO
  • Publication number: 20090115044
    Abstract: Methods and structures for stack type semiconductor packaging are disclosed. In one embodiment, a semiconductor device includes a semiconductor chip mounted onto a substrate, a first resin molding portion formed on the substrate for sealing the semiconductor chip, and a through metal mounted on the substrate so as to pierce the first resin molding portion around the semiconductor chip. The semiconductor device further comprises an upper metal electrically coupled with the through metal and mounted on the first resin molding portion to extend from the through metal toward the semiconductor chip along an upper surface of the first resin molding portion, where the through metal and the upper metal are formed into an integral structure.
    Type: Application
    Filed: April 25, 2008
    Publication date: May 7, 2009
    Inventors: Masataka HOSHINO, Masahiko HARAYAMA, Koji TAYA, Naomi MASUDA, Masanori ONODERA, Ryota FUKUYAMA
  • Publication number: 20090093085
    Abstract: A carrier structure for fabricating a stacked-type semiconductor device includes: a lower carrier that has laminated thin plates and has first openings for mounting first semiconductor packages thereon; and an upper carrier having second openings for mounting second semiconductor packages on the first semiconductor packages. The lower carrier composed of the laminated thin plates realizes an even plate thickness and reduces warps because stress is distributed to the thin plates. This results in an improved production yield. A pattern of the openings in the thin plates of the lower carrier may be formed by etching or electric discharging. The openings thus formed have reduced warps and burrs.
    Type: Application
    Filed: December 3, 2008
    Publication date: April 9, 2009
    Inventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka
  • Patent number: 7489029
    Abstract: A carrier structure for fabricating a stacked-type semiconductor device includes: a lower carrier that has laminated thin plates and has first openings for mounting first semiconductor packages thereon; and an upper carrier having second openings for mounting second semiconductor packages on the first semiconductor packages. The lower carrier composed of the laminated thin plates realizes an even plate thickness and reduces warps because stress is distributed to the thin plates. This results in an improved production yield. A pattern of the openings in the thin plates of the lower carrier may be formed by etching or electric discharging. The openings thus formed have reduced warps and burrs.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: February 10, 2009
    Assignee: Spansion LLC
    Inventors: Masanori Onodera, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Koji Taya, Junji Tanaka
  • Publication number: 20090008747
    Abstract: A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.
    Type: Application
    Filed: July 1, 2008
    Publication date: January 8, 2009
    Inventors: Masataka Hoshino, Ryoto Fukuyama, Koji Taya
  • Publication number: 20080274591
    Abstract: A carrier for a stacked-type semiconductor device includes an accommodating section for accommodating stacked semiconductor devices, guide portions guiding the stacked semiconductor devices, and grooves through which a fluid may flow to the accommodating section and to sides of the stacked semiconductor devices. These grooves facilitate the flow of gas or liquid on the sides of the accommodating sections, and it is thus expected that the flow of hot wind during the reflow process and cleaning liquid during the cleaning process can be facilitated. This improves the production yield and the cleaning effects. Holes for connecting the accommodating section to the outside may be provided at corners of the accommodating section. Gas may be guided from the lower side of the accommodating section, so that heat can be efficiently applied to the semiconductor devices and bonding failures therebetween can be reduced.
    Type: Application
    Filed: July 1, 2008
    Publication date: November 6, 2008
    Inventors: Koji Taya, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Masanori Onodera, Junji Tanaka, Murugasan Manikam Achari
  • Patent number: 7414305
    Abstract: A carrier for a stacked-type semiconductor device includes an accommodating section for accommodating stacked semiconductor devices, guide portions guiding the stacked semiconductor devices, and grooves through which a fluid may flow to the accommodating section and to sides of the stacked semiconductor devices. These grooves facilitate the flow of gas or liquid on the sides of the accommodating sections, and it is thus expected that the flow of hot wind during the reflow process and cleaning liquid during the cleaning process can be facilitated. This improves the production yield and the cleaning effects. Holes for connecting the accommodating section to the outside may be provided at corners of the accommodating section. Gas may be guided from the lower side of the accommodating section, so that heat can be efficiently applied to the semiconductor devices and bonding failures therebetween can be reduced.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: August 19, 2008
    Assignee: Spansion LLC
    Inventors: Koji Taya, Kouichi Meguro, Junichi Kasai, Yasuhiro Shinma, Masanori Onodera, Junji Tanaka, Murugasan Manikam Achari
  • Publication number: 20080169544
    Abstract: A method of fabricating a semiconductor device includes: mounting a semiconductor chip on a substrate; forming an upper connection terminal on a side of the substrate on which the semiconductor chip is mounted; forming a resin seal portion that seals the semiconductor chip and the upper connection terminal so that an upper surface of the upper connection terminal is exposed; and shaping the upper connection terminal so that the upper surface of the upper connection terminal becomes lower than an upper surface of the resin seal portion.
    Type: Application
    Filed: January 17, 2007
    Publication date: July 17, 2008
    Inventors: Junji Tanaka, Junichi Kasai, Kouichi Meguro, Masanori Onodera, Koji Taya
  • Publication number: 20080169552
    Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.
    Type: Application
    Filed: January 17, 2007
    Publication date: July 17, 2008
    Inventors: Koji Taya, Masanori Onodera, Junji Tanaka, Kouichi Meguro