Patents by Inventor Koji Torii
Koji Torii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240055323Abstract: A semiconductor device assembly including a through-silicon via (TSV) having an end region protruding from a back side of the substrate, the end region being surrounded by a conductive annulus disposed over the back side of the substrate; a dielectric layer disposed over the back side of the substrate, the dielectric layer having an upper surface flush with an upper surface of the end region of the TSV and flush with an upper surface of the conductive annulus; and a bond pad disposed over and electrically coupled to the end region of the TSV and the conductive annulus.Type: ApplicationFiled: August 9, 2022Publication date: February 15, 2024Inventors: Ren Yuan Huang, Kuan Wei Tseng, Te Pao, Koji Torii
-
Patent number: 9117829Abstract: A semiconductor device includes a semiconductor substrate having a peripheral edge, a first surface, and a second surface opposite to the first surface, an inter-layer insulator including a guard ring formed on the first surface, adjacent to the peripheral edge of the semiconductor substrate, a first groove formed on the second surface, adjacent to the peripheral edge of the semiconductor substrate, and a through electrode penetrating the second surface to the inter-layer insulator near the groove and on an opposite side of the groove with respect to the peripheral edge.Type: GrantFiled: December 23, 2013Date of Patent: August 25, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Akira Ide, Koji Torii
-
Patent number: 8981532Abstract: In a semiconductor device, the thickness of an insulating film formed in a through hole is reduced, while an annular groove having an insulating material embedded therein is provided so as to ensure a sufficient total thickness of the insulator, whereby a through silicon via is provided with an insulating ring which is improved in both processability and functionality.Type: GrantFiled: November 8, 2012Date of Patent: March 17, 2015Assignee: PS4 Luxco S.a.r.l.Inventor: Koji Torii
-
Patent number: 8930094Abstract: A control device for a hydraulic winch includes: a hydraulic source; a variable-displacement hydraulic motor; a winch operation member; an accelerator operation quantity detection unit; an engine control unit; a rotation speed detection unit; a line pull detection unit; a condition decision unit; and a motor displacement control unit, wherein: once the condition decision unit decides that the fuel-efficient, high-speed operation condition has been established, the engine control unit sets an upper limit to the engine rotation speed at a predetermined rotation speed, lower than the maximum rotation speed.Type: GrantFiled: May 14, 2013Date of Patent: January 6, 2015Assignee: Hitachi Sumitomo Heavy Industries Construction Crane Co., Ltd.Inventor: Koji Torii
-
Patent number: 8921984Abstract: In a connecting portion between an interconnection and a first bump which is a part of a through electrode penetrating a semiconductor chip and which penetrates a semiconductor substrate, a protruding portion protruding from the interconnection to the side of the first bump is provided. The protruding portion may be made of an insulating material and may be made of a conductive material.Type: GrantFiled: May 20, 2013Date of Patent: December 30, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Koji Torii, Nobuyuki Nakamura
-
Publication number: 20140183704Abstract: A method of manufacturing a semiconductor device including a semiconductor substrate having first and second surfaces and a peripheral edge, the first and second surfaces being opposite to each other, includes forming an inter-layer insulator having a guard ring on the first surface, adjacent to the peripheral edge, forming a first groove on the second surface and adjacent to the peripheral edge, and forming a through electrode that penetrates the second surface to the inter-layer insulator near the first groove and on an opposite side of the groove with respect to the peripheral edge.Type: ApplicationFiled: December 23, 2013Publication date: July 3, 2014Applicant: Elpida Memory, Inc.Inventors: Akira Ide, Koji Torii
-
Patent number: 8633593Abstract: A semiconductor device includes a semiconductor substrate; and a through electrode that penetrates the semiconductor substrate. The semiconductor substrate has a groove structure that is positioned between a peripheral edge of the semiconductor substrate and the through electrode.Type: GrantFiled: March 22, 2012Date of Patent: January 21, 2014Assignee: Elpida Memory, Inc.Inventors: Akira Ide, Koji Torii
-
Publication number: 20130313689Abstract: In a connecting portion between an interconnection and a first bump which is a part of a through electrode penetrating a semiconductor chip and which penetrates a semiconductor substrate, a protruding portion protruding from the interconnection to the side of the first bump is provided. The protruding portion may be made of an insulating material and may be made of a conductive material.Type: ApplicationFiled: May 20, 2013Publication date: November 28, 2013Applicant: Elpida Memory, Inc.Inventors: Koji TORII, Nobuyuki NAKAMURA
-
Publication number: 20130311051Abstract: A control device for a hydraulic winch includes: a hydraulic source; a variable-displacement hydraulic motor; a winch operation member; an accelerator operation quantity detection unit; an engine control unit; a rotation speed detection unit; a line pull detection unit; a condition decision unit; and a motor displacement control unit, wherein: once the condition decision unit decides that the fuel-efficient, high-speed operation condition has been established, the engine control unit sets an upper limit to the engine rotation speed at a predetermined rotation speed, lower than the maximum rotation speed.Type: ApplicationFiled: May 14, 2013Publication date: November 21, 2013Applicant: Hitachi Sumitomo Heavy Industries Construction Crane Co., Ltd.Inventor: Koji TORII
-
Publication number: 20120241917Abstract: A semiconductor device includes a semiconductor substrate; and a through electrode that penetrates the semiconductor substrate. The semiconductor substrate has a groove structure that is positioned between a peripheral edge of the semiconductor substrate and the through electrode.Type: ApplicationFiled: March 22, 2012Publication date: September 27, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Akira IDE, Koji Torii
-
Patent number: 7722439Abstract: A semiconductor device manufacturing apparatus according to the present invention comprises a head for holding a semiconductor wafer, a retainer ring for surrounding the outer periphery of the semiconductor wafer held by the head, and a polishing pad for polishing a polished surface of the semiconductor wafer. This apparatus presses the polished surface of the semiconductor wafer against the polishing pad together with the retainer ring to polish the semiconductor wafer. The retainer ring used in the present invention has a surface that is in contact with the polishing pad, which increases a contact area of the retainer ring against the polishing pad in accordance with wear of the retainer ring.Type: GrantFiled: December 5, 2007Date of Patent: May 25, 2010Assignee: Elpida Memory, Inc.Inventor: Koji Torii
-
Publication number: 20080146123Abstract: A semiconductor device manufacturing apparatus according to the present invention comprises a head for holding a semiconductor wafer, a retainer ring for surrounding the outer periphery of the semiconductor wafer held by the head, and a polishing pad for polishing a polished surface of the semiconductor wafer. This apparatus presses the polished surface of the semiconductor wafer against the polishing pad together with the retainer ring to polish the semiconductor wafer. The retainer ring used in the present invention has a surface that is in contact with the polishing pad, which increases a contact area of the retainer ring against the polishing pad in accordance with wear of the retainer ring.Type: ApplicationFiled: December 5, 2007Publication date: June 19, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Koji TORII
-
Publication number: 20070281485Abstract: A semiconductor device fabrication method by which a semiconductor wafer is polished by pressing the semiconductor wafer against a polishing pad includes: an optimum condition calculation step for finding polishing conditions based on the hardness of the polishing pad; and a step of polishing the semiconductor wafer according to the polishing conditions that have been found.Type: ApplicationFiled: May 31, 2007Publication date: December 6, 2007Applicant: ELPIDA MEMORY, INC.Inventor: Koji Torii
-
Publication number: 20070243796Abstract: A wear thickness for a retainer ring is measured at a specified timing. The height of the retainer ring or the polishing condition of the polishing apparatus is changed in an amount greater than or equal to the wear thickness of the retainer ring. This compensates for the wear thickness of the retainer ring which degrades the within wafer uniformity of polishing rate due to a change in the bottom surface of the retainer ring.Type: ApplicationFiled: April 12, 2007Publication date: October 18, 2007Applicant: ELPIDA MEMORY, INC.Inventor: Koji TORII
-
Patent number: 6965599Abstract: A packet relay apparatus is disposed that relays packets between an inside node and an outside IP network. A class processing unit classifies send packets to be relayed to the IP network and allocates different virtual IP addresses thereto. A send packet relay unit translates source addresses of the send packets to be relayed to the IP network into virtual IP addresses on a class by class basis, to establish classified IP communication paths. For reply packets from the IP network passing through communication paths on a class by class basis, a reply packet relay unit inversely translates destination virtual IP addresses into original addresses by reference to the results of address translation effected by the send packet relay unit.Type: GrantFiled: November 17, 2000Date of Patent: November 15, 2005Assignee: Fujitsu LimitedInventors: Hideshi Sakurai, Koji Torii
-
Publication number: 20050209528Abstract: In a display section, a measured value of information of a living body is displayed on a measured data display section, and a figure representing a human body including body parts such as arm and leg is displayed on a body display section. For example, a percentage of muscle and a percentage of body fat measured 30 days ago and a current percentage of muscle and percentage of body fat are compared with each other, and respective increase/decrease values are displayed on the measured data display section as well as the measured values. Further, a color of illumination in the background of the body display section is changed depending on a degree of the increase/decrease value. For example, the background of the body display section is illuminated in red when the percentage of muscle is decreased by a % or more, blue when increased by a % or more, and green when a percentage of variation is less than a % in comparing current data with data measured 30 days ago.Type: ApplicationFiled: March 15, 2005Publication date: September 22, 2005Applicant: Omron Healthcare Co., Ltd.Inventors: Tetsuya Sato, Koji Torii
-
Patent number: 6432825Abstract: To provide a semiconductor device production method capable of solving the problem of the latent period of time in which polishing is hardly performed immediately after a polishing start. In order to reduce the latent period of time caused immediately after a metal film polishing start, the polishing process is preceded by an oxide removal step for removing oxide from an object to be polished.Type: GrantFiled: November 23, 1999Date of Patent: August 13, 2002Assignee: NEC CorporationInventor: Koji Torii
-
Publication number: 20020068451Abstract: To provide a semiconductor device production method capable of solving the problem of the latent period of time in which polishing is hardly performed immediately after a polishing start. In order to reduce the latent period of time caused immediately after a metal film polishing start, the polishing process is preceded by an oxide removal step for removing oxide from an object to be polished.Type: ApplicationFiled: November 23, 1999Publication date: June 6, 2002Inventor: KOJI TORII
-
Patent number: 6213847Abstract: A semiconductor wafer polishing device is capable of improving controllability of a residual layer thickness and improving a production ability. The semiconductor wafer polishing device performs polishing of an interlayer insulation layer on a semiconductor wafer by performing divided polishing for the interlayer insulation layer by means of a platen, measuring a layer thickness of the interlayer insulation layer during a polishing process by the platen, and performing final polishing depending upon a result of measurement.Type: GrantFiled: May 14, 1999Date of Patent: April 10, 2001Assignee: NEC CorporationInventor: Koji Torii
-
Patent number: D504632Type: GrantFiled: April 25, 2003Date of Patent: May 3, 2005Assignee: Omron CorporationInventors: Shin Nishiura, Koji Torii, Nobuo Kubo, Hiroshi Ogawa