Patents by Inventor Koji Yamazaki

Koji Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250033507
    Abstract: Implementations generally relate to electric vehicle charging station synchronization. In some implementations, a method includes computing a target charging time to charge a battery of an electric vehicle. The method further includes computing a total play length of one or more media items. The method further includes synchronizing the target charging time with the total play length. The method further includes playing the one or more media items in the electric vehicle while the battery of the electric vehicle is being charged.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 30, 2025
    Applicant: Sony Group Corporation
    Inventors: Tatsuya Yamazaki, Tetsugoro Ihara, Koji Nagata, Naomasa Takahashi, Tatsushi Nashida, Tonni Sandager Larsen
  • Patent number: 12212023
    Abstract: A cell stack device includes a cell stack and an end current collector. The cell stack includes a plurality of cells arrayed therein. The end current collector is located in an end portion of the cell stack in an array direction of the plurality of cells. The end current collector includes a surface exposed to an oxidizing atmosphere covered with a covering material including manganese and a surface exposed to a reducing atmosphere covered with a film different from the covering material.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: January 28, 2025
    Assignee: Kyocera Corporation
    Inventors: Koji Yamazaki, Fumito Furuuchi
  • Publication number: 20250031549
    Abstract: A display device having both a touch detection function and a function of capturing an image of a shape of a fingerprint or a vein is provided. The display device includes a first substrate, a first light-emitting element, a second light-emitting element, a light-receiving element, a light-blocking layer, a first resin layer, and a second resin layer. The first light-emitting element and the light-receiving element are arranged over the first substrate, and the first resin layer is provided over the first light-emitting element and the light-receiving element. The light-blocking layer is provided over the first resin layer, and the second light-emitting element is provided over the light-blocking layer. The second resin layer is provided over the second light-emitting layer. The first light-emitting element emits visible light upward, and the second light-emitting element emits invisible light upward.
    Type: Application
    Filed: October 9, 2024
    Publication date: January 23, 2025
    Inventors: Shunpei YAMAZAKI, Shingo EGUCHI, Daisuke KUBOTA, Koji KUSUNOKI, Kazunori WATANABE
  • Patent number: 12136582
    Abstract: A power module is obtained in which the thermal resistance in the range from a semiconductor device to a base plate is reduced and the stress in the joining portion is relieved. The power module includes at least one semiconductor device, an insulating substrate having an insulating layer, a circuit layer provided on an upper surface of the insulating layer and a metal layer provided on a lower surface of the insulating layer, and a sintering joining member with an upper surface larger in outer circumference than a back surface of the at least one semiconductor device, to join together the back surface of the at least one semiconductor device and an upper surface of the circuit layer on an upper-surface side of the insulating layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: November 5, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoshinori Yokoyama, Tetsu Negishi, Koji Yamazaki
  • Publication number: 20240312386
    Abstract: A display driver includes a plurality of DA conversion circuits, amplifiers, and a switch circuit. Each of the DA conversion circuits outputs a gradation reference voltage in a gradation reference voltage group generated by one of gradation reference voltage generating circuits as a gradation voltage. The amplifiers each output a voltage output a voltage obtained by amplifying each gradation voltage as an output voltage. The switch circuit receives an output voltage group output from the amplifiers and a gradation voltage group generated by the respective DA conversion circuits coupled to a specific gradation reference voltage generating circuit. The switch circuit outputs the output voltage group to the display panel when a normal display mode while outputting the gradation voltage group to the display panel when a monochromatic display mode.
    Type: Application
    Filed: March 11, 2024
    Publication date: September 19, 2024
    Inventor: Koji Yamazaki
  • Patent number: 12076967
    Abstract: Provided is a metal joint (5) including: a Ag—Cu—Zn layer (7); and Cu—Zn layers (6) joined to both surfaces of the Ag—Cu—Zn layer (7), wherein the Ag—Cu—Zn layer (7) has a composition in which a Cu component is 1 atm % or more and 10 atm % or less, a Zn component is 1 atm % or more and 40 atm % or less, and the balance is a Ag component with respect to the total 100 atm %, and wherein the Cu—Zn layers (6) have a composition in which a Zn component is 10 atm % or more and 40 atm % or less and the balance is a Cu component with respect to the total 100 atm %. It is therefore possible to obtain the metal joint (5), which is capable of joining metal base materials to each other without being limited to aluminum-based materials, and also have high mechanical strength.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 3, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takashi Ijima, Koji Yamazaki
  • Publication number: 20240105535
    Abstract: In this semiconductor device, a terminal having a first metal electrode portion at an upper surface is joined via a first joining material to an upper surface of a semiconductor element. The terminal and the semiconductor element are sealed by a sealing material so that an upper surface of the first metal electrode portion is exposed. The upper surface of the first metal electrode portion is connected via a second joining material to a lower surface of a second metal electrode portion formed at a lower surface of a circuit board. Slopes are provided on an upper surface of the sealing material so that vertical-direction height at the first metal electrode portion is the largest and vertical-direction height at an end of the sealing material is low.
    Type: Application
    Filed: March 17, 2021
    Publication date: March 28, 2024
    Applicant: Mitsubishi Electric Corporation
    Inventor: Koji YAMAZAKI
  • Publication number: 20240091909
    Abstract: Provided is a surface treatment member used by being mounted on a rotary member in a surface treatment system including the rotary member. The surface treatment member includes: a base; a striking member having an annular body portion and a protruding portion that protrudes from the body portion; and a shaft member disposed in a region on an inner side of the body portion. When the surface treatment member is viewed along an imaginary axis about which the base is to be rotated, a portion of the striking member is exposed outside an outer periphery of the base by a centrifugal force when the surface treatment member is rotated, and an entirety of the striking member is retractable toward inside an imaginary circle that passes over an outermost periphery of the base about the imaginary axis after the striking member impinges on a surface treatment object.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventor: Koji YAMAZAKI
  • Patent number: 11764183
    Abstract: Provided is a joint structure interposed between a semiconductor element and a substrate, the joint structure including: a Sn phase; Cu alloy particles containing P in an amount of 1 mass % or more and less than 7 mass %; and Ag particles, wherein the Cu alloy particles are each coated with a Cu6Sn5 layer, wherein the Ag particles are each coated with a Ag3Sn layer, wherein the Cu alloy particles and the Ag particles are at least partially bonded to each other through a Cu10Sn3 phase, wherein a total of addition amounts of the Cu alloy particles and the Ag particles is 25 mass % or more and less than 65 mass % with respect to the joint structure, and wherein a mass ratio of the addition amount of the Ag particles to the addition amount of the Cu alloy particles is 0.2 or more and less than 1.2.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: September 19, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Koji Yamazaki, Yoshio Tamura
  • Patent number: 11720080
    Abstract: An optimum combination of a loop unrolling number and a circuit parallel number in a high-level synthesis is determined. A circuit synthesis information generation unit sets, as parameter candidates, a plurality of combinations of a loop unrolling number and a circuit parallel number to generate circuit synthesis information indicating a synthesis circuit obtained by high-level synthesis processing for each of the combinations. An optimum parameter determination unit calculates, for each piece of the generated circuit synthesis information, an estimation processing performance related to the synthesis circuit indicated by the circuit synthesis information, and determines an optimum combination of the loop unrolling number and the circuit parallel number based on the circuit synthesis information based on which a maximum estimation processing performance is obtained.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: August 8, 2023
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Syuhei Yoshida, Yuta Ukon, Koji Yamazaki, Koyo Nitta
  • Publication number: 20230115289
    Abstract: In a semiconductor device according to the present disclosure, one end and the other end of a plurality of insulation covering wires are joined to a connection region in an upper electrode of a DBC substrate over a semiconductor element while an insulation covering portion in a center region has contact with a surface of the semiconductor element. The plurality of insulation covering wires are provided along an X direction in the same manner as the plurality of metal wires. The plurality of insulation covering wires are provided with no loosening, thus have press force of pressing the semiconductor element in a direction of the solder joint portion.
    Type: Application
    Filed: May 14, 2020
    Publication date: April 13, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventor: Koji YAMAZAKI
  • Publication number: 20230109696
    Abstract: The present invention provides a coating composition wherein the coating composition comprises the following components (A) and (B): (A) an emulsion of a silicone acrylic copolymer resin having a glass transition temperature of 0° C. or higher and being a copolymer of 40 to 90 parts by mass of (a1) a polyorganosiloxane represented by the formula (1) with 10 to 60 parts by mass of (a2) a methacrylic acid ester monomer, provided that a total amount of components (a1) and (a2) is 100 parts by mass; the emulsion being in an amount of 5 to 80 parts by mass as a solid content, and (B) a metal oxide in an amount of 20 to 95 parts by mass, provided that a total mass of the solid content of component (A) and component (B) is 100 parts by mass.
    Type: Application
    Filed: September 22, 2022
    Publication date: April 13, 2023
    Inventors: Koji Yamazaki, Kentaro Watanabe
  • Patent number: 11619291
    Abstract: A differential device is provided with: a ring gear having a tooth row arranged around an axis to mesh with an input gear; an outer case combined with the ring gear and rotatable about the axis; an inner case rotatable about the axis relative to the outer case and having a toothed end with axially projecting dog teeth; a differential gear set supported by the inner case and to be coupled with a pair of axles to allow differential motion between the axles; a clutch member engaging with the outer case and disconnectably connecting with the dog teeth so as to prevent the inner case from rotating relative to the outer case; and perforations penetrating the outer case and opened on an outer face of the outer case, the perforations being so disposed as to expose the dog teeth radially outwardly from the outer case.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: April 4, 2023
    Assignee: GKN Automotive Limited
    Inventors: Kazuhiro Ohashi, Hideki Nonaka, Koji Yamazaki
  • Publication number: 20230054798
    Abstract: Provided is a metal jointed body, joined by solid-phase joining in the atmosphere, in which no protrusion of molten joining material occurs, that improves dimensional stability. A metal jointed body is formed by (A) making Ag films of two metal laminated bodies opposed to each other, the metal jointed body being configured by sequentially laminating a Zn film and an Ag film on an Al substrate serving as a member to be joined, and (B) bringing the Ag films into contact with each other, then (C) heating is performed while pressurizing, and closely adhering and solid-phase joining the Ag films to each other. The completed metal jointed body is a portion where Al—Ag alloy layers are provided on both sides of an Ag—Zn—Al alloy layer to join the Al substrates to each other.
    Type: Application
    Filed: March 27, 2020
    Publication date: February 23, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takashi IJIMA, Koji YAMAZAKI
  • Publication number: 20220415747
    Abstract: A power module is obtained in which the thermal resistance in the range from a semiconductor device to a base plate is reduced and the stress in the joining portion is relieved. The power module includes at least one semiconductor device, an insulating substrate having an insulating layer, a circuit layer provided on an upper surface of the insulating layer and a metal layer provided on a lower surface of the insulating layer, and a sintering joining member with an upper surface larger in outer circumference than a back surface of the at least one semiconductor device, to join together the back surface of the at least one semiconductor device and an upper surface of the circuit layer on an upper-surface side of the insulating layer.
    Type: Application
    Filed: December 26, 2019
    Publication date: December 29, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yoshinori YOKOYAMA, Tetsu NEGISHI, Koji YAMAZAKI
  • Publication number: 20220376271
    Abstract: A cell stack device includes a cell stack and an end current collector. The cell stack includes a plurality of cells arrayed therein. The end current collector is located in an end portion of the cell stack in an array direction of the plurality of cells. The end current collector includes a surface exposed to an oxidizing atmosphere covered with a covering material including manganese and a surface exposed to a reducing atmosphere covered with a film different from the covering material.
    Type: Application
    Filed: October 8, 2020
    Publication date: November 24, 2022
    Inventors: Koji YAMAZAKI, Fumito FURUUCHI
  • Patent number: 11496400
    Abstract: A network load balancing apparatus has a data buffer for each communication path of a received packet's transfer destinations, calculates a first hash value using a field value contained in the packet, determines, based on the field value of the packet or the first hash value, a communication path of a transfer destination of the packet subject to external transfer control for transmission to a predetermined external server, determines, based on the first hash value, a communication path of a transfer destination of the packet to be subject to priority control, determines, based on a second hash value based on the first hash value, a communication path of a transfer destination of the packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, and transmits the packet to a data buffer corresponding to the communication path of the transfer destination.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: November 8, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Koji Yamazaki, Saki Hatta, Shoko Oteru, Tomoaki Kawamura, Yuta Ukon, Shuhei Yoshida, Koyo Nitta
  • Patent number: 11451479
    Abstract: A network load balancing apparatus has a data buffer provided to each communication path of transfer destinations of a received packet and being associated with a virtual function, determines a destination virtual function based on a field value of the received packet, determines a communication path of a transfer destination of a packet to be subject to priority control based on a first hash value calculated using the field value, determines a communication path of a transfer destination of a packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, based on a second hash value based on the first hash value, and transmits the packet to a data buffer corresponding to the destination virtual function and the communication path of the transfer destination.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: September 20, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Saki Hatta, Shoko Oteru, Tomoaki Kawamura, Koji Yamazaki, Takahiro Hatano
  • Patent number: 11321255
    Abstract: A packet processing apparatus includes a line adapter configured to receive packets from a communication line, a packet combining unit configured to generate a combined packet by combining a plurality of packets received from the communication line, a packet memory configured to store packets received from the communication line, and a combined packet transferring unit configured to DMA transfer the combined packet generated by the packet combining unit to the packet memory. The combined packet transferring unit determines an address of start data of each packet inside the combined packet on the packet memory, writes information on the address into the descriptor that is a predetermined data area on a memory, and DMA transfers the combined packet to the packet memory.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 3, 2022
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Tomoaki Kawamura, Saki Hatta, Shoko Oteru, Koji Yamazaki, Takahiro Hatano
  • Patent number: 11196684
    Abstract: A flow control device includes an analysis unit identifying a flow of a received packet, a plurality of queues temporarily storing packets sorted according to each flow, an allocation information storage unit storing allocation information regarding a queue allocated for each flow, a sorting unit deciding a queue to be a storage destination of the received packet and sorts the packet based on a result identified by the analysis unit and the allocation information, a saved packet holding unit saving a packet belonging to a flow determined to have no allocation information regarding the queue to be allocated by the sorting unit, and a transmission unit transmitting the packet temporarily stored in the plurality of queues and the packet saved in the saved packet holding unit to a processing unit that processes a packet.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: December 7, 2021
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Syuhei Yoshida, Yuta Ukon, Koji Yamazaki, Koyo Nitta