Patents by Inventor Kojiro Shiraishi

Kojiro Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10559695
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: February 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10543655
    Abstract: There is provided a binding member. An upper toothed part having projections and recesses for forming irregularities in a bundle of recording materials. A lower toothed part having projections and recesses for forming irregularities in the bundle of recording materials and forming a pair with the upper toothed part. In at least one of the upper toothed part and the lower toothed part, in a cross section shape of the toothed part, the recesses of the toothed part have depressed areas depressed from virtual lines which are extensions of inclined surfaces of the toothed part.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 28, 2020
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Hiroaki Awano, Yoshinori Nakano, Takuya Makita, Junichi Hirota, Hiroshi Hagiwara, Emiko Shiraishi, Yasuhiro Kusumoto, Kojiro Tsutsumi, Toshiyasu Yukawa, Katsumi Harada
  • Patent number: 10421306
    Abstract: There is provided a binding member. The binding member includes: an upper toothed part having projections and recesses for forming irregularities in a bundle of recording materials; and a lower toothed part having projections and recesses for forming irregularities in the bundle of recording materials and forming a pair with the upper toothed part. In at least one of the upper toothed part and the lower toothed part, in side surfaces of the recesses of one toothed part, when the upper toothed part and the lower toothed part are engaged, surfaces wide in a direction parallel to the pressing direction of the toothed parts are formed so as to be provided gaps between the upper toothed part and the lower toothed part.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: September 24, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Hiroaki Awano, Yoshinori Nakano, Takuya Makita, Junichi Hirota, Hiroshi Hagiwara, Emiko Shiraishi, Yasuhiro Kusumoto, Kojiro Tsutsumi, Toshiyasu Yukawa, Katsumi Harada
  • Patent number: 10406843
    Abstract: In a cross section shape of the toothed part, in gaps formed between a recesses and a projections when a upper toothed part and a lower toothed part are engaged without a bundle of recording materials, when the distances between the recesses and the projections in a pressing direction of the toothed part at positions where the distances from a center lines of the projections in a direction perpendicular to the pressing direction of the toothed part to the surfaces of the projections in the direction perpendicular to the pressing direction of the toothed part are a distance L1 are H1, and the distances between the recesses and the projections at positions where the distances from the center lines to surfaces of the projections in the direction perpendicular to the pressing direction of the toothed part are H2, a combination of L1 and L2 satisfies H1 is smaller than H2.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: September 10, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Hiroaki Awano, Yoshinori Nakano, Takuya Makita, Junichi Hirota, Hiroshi Hagiwara, Emiko Shiraishi, Yasuhiro Kusumoto, Kojiro Tsutsumi, Toshiyasu Yukawa, Katsumi Harada
  • Patent number: 10357932
    Abstract: There is provided a binding member. The binding member includes an upper toothed part having projections and recesses for forming irregularities in a bundle of recording materials; and a lower toothed part having projections and recesses for forming irregularities in the bundle of recording materials and forming a pair with the upper toothed part. In at least one of the upper toothed part and the lower toothed part, in some of parts of inclined surfaces of the toothed part which form the recesses, second curved surfaces having the centers of curvature on the opposite sides of the inclined surfaces to the centers of curvature of first curved surfaces which form the recesses are formed.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: July 23, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Hiroaki Awano, Yoshinori Nakano, Takuya Makita, Junichi Hirota, Hiroshi Hagiwara, Emiko Shiraishi, Yasuhiro Kusumoto, Kojiro Tsutsumi, Toshiyasu Yukawa, Katsumi Harada
  • Patent number: 10326025
    Abstract: To provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability and a manufacturing method of the semiconductor device with high mass productivity. The summary is that an inverted-staggered (bottom-gate) thin film transistor is included in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, a channel protective layer is provided in a region that overlaps a channel formation region of the semiconductor layer, and a buffer layer is provided between the semiconductor layer and source and drain electrodes. An ohmic contact is formed by intentionally providing the buffer layer having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrodes.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 18, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20190157461
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 23, 2019
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Patent number: 9917197
    Abstract: An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: March 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takafumi Mizoguchi, Kojiro Shiraishi, Masashi Tsubuku
  • Patent number: 9859441
    Abstract: In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: January 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20170323957
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20170236943
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Patent number: 9666719
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: May 30, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20170033228
    Abstract: In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 2, 2017
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20160380111
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Application
    Filed: September 13, 2016
    Publication date: December 29, 2016
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20160336459
    Abstract: An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.
    Type: Application
    Filed: July 26, 2016
    Publication date: November 17, 2016
    Inventors: Takafumi MIZOGUCHI, Kojiro SHIRAISHI, Masashi TSUBUKU
  • Patent number: 9496406
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: November 15, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 9437743
    Abstract: An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: September 6, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takafumi Mizoguchi, Kojiro Shiraishi, Masashi Tsubuku
  • Patent number: 9412798
    Abstract: In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: August 9, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 9276124
    Abstract: Provided is a method for manufacturing a semiconductor device so as not expose a semiconductor layer to moisture and the number of masks is reduced. For example, a first conductive film, a first insulating film, a semiconductor film, a second conductive film, and a mask film are formed. The first mask film is processed to form a first mask layer. Dry etching is performed on the first insulating film, the semiconductor film, and the second conductive film with the use of the first mask layer to form a thin film stack body, so that a surface of the first conductive film is at least exposed. Sidewall insulating layers covering side surfaces of the thin film stack body are formed. The first conductive film is side-etched to form a first electrode. A second electrode layer is formed with the second mask layer.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: March 1, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takafumi Mizoguchi, Kojiro Shiraishi
  • Publication number: 20150349099
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Application
    Filed: August 6, 2015
    Publication date: December 3, 2015
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI