Patents by Inventor Kojiro Shiraishi

Kojiro Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230113633
    Abstract: The present invention relates to a medical Au-Pt-Pd alloy including Au, Pt,Pd, and inevitable impurities. The Au-Pt-Pd alloy has an alloy compositioninside a polygon (A1-A2-A3-A4) surrounded by straight lines connected at pointA1 (Au: 53 atom%, Pt: 4 atom%, and Pd: 43 atom%), point A2 (Au: 70 atom%,Pt: 4 atom%, and Pd: 26 atom%), point A3 (Au: 69.9 atom%, Pt: 30 atom%, and Pd: 0.1 atom%), and point A4 (Au: 49.9 atom%, Pt: 50 atom%, and Pd: 0.1 atom%) in a Au-Pt-Pd ternary state diagram. In a metal structure of the alloy, at least one of a Au-rich phase and a Pt-rich phase is distributed, and the total of the area ratio of the Au-rich phase and the area ratio of the Pt-rich phase is 1.5% or more and 25.4% or less.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 13, 2023
    Applicants: TANAKA KIKINZOKU KOGYO K.K., TOKUSHIMA UNIVERSITY
    Inventors: Michimasa OKUBO, Kenji GOTO, Kunihiro TANAKA, Kojiro SHIRAISHI, Kunihiro SHIMA, Yuya KATO, Kenichi HAMADA, Eiichi HONDA, Emi TAKEGAWA
  • Patent number: 11453931
    Abstract: The present invention relates to a medical Au—Pt—Pd alloy including Au, Pt, Pd, and inevitable impurities. The alloy has an alloy composition inside a polygon (A1-A2-A3-A4-A5-A6) surrounded by straight lines connected at point A1 (Au: 37.9 atom %, Pt: 0.1 atom %, and Pd: 62 atom %), point A2 (Au: 79.9 atom %, Pt: 0.1 atom %, and Pd: 20 atom %), point A3 (Au: 79.9 atom %, Pt: 20 atom %, and Pd: 0.1 atom %), point A4 (Au: 69.9 atom %, Pt: 30 atom %, and Pd: 0.1 atom %), point A5 (Au: 49 atom %, Pt: 30 atom %, and Pd: 21 atom %), and point A6 (Au: 39 atom %, Pt: 40 atom %, and Pd: 21 atom %) in a Au—Pt—Pd ternary state diagram. The metal structure of the alloy is optimized, and the metal structure is close to a single-phase structure, and has little precipitation of a Au-rich phase and a Pt-rich phase different in composition from a mother phase.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: September 27, 2022
    Assignees: TANAKA KIKINZOKU KOGYO K.K., TOKUSHIMA UNIVERSITY
    Inventors: Michimasa Okubo, Kenji Goto, Kunihiro Tanaka, Kojiro Shiraishi, Kunihiro Shima, Yuya Kato, Kenichi Hamada, Eiichi Honda, Emi Takegawa
  • Publication number: 20220213576
    Abstract: The present invention relates to a medical Au—Pt—Pd alloy including Au, Pt, Pd, and inevitable impurities. The alloy has an alloy composition inside a polygon (A1-A2-A3-A4-A5-A6) surrounded by straight lines connected at point A1 (Au: 37.9 atom %, Pt: 0.1 atom %, and Pd: 62 atom %), point A2 (Au: 79.9 atom %, Pt: 0.1 atom %, and Pd: 20 atom %), point A3 (Au: 79.9 atom %, Pt: 20 atom %, and Pd: 0.1 atom %), point A4 (Au: 69.9 atom %, Pt: 30 atom %, and Pd: 0.1 atom %), point A5 (Au: 49 atom %, Pt: 30 atom %, and Pd: 21 atom %), and point A6 (Au: 39 atom %, Pt: 40 atom %, and Pd: 21 atom %) in a Au—Pt—Pd ternary state diagram. The metal structure of the alloy is optimized, and the metal structure is close to a single-phase structure, and has little precipitation of a Au-rich phase and a Pt-rich phase different in composition from a mother phase.
    Type: Application
    Filed: September 24, 2020
    Publication date: July 7, 2022
    Applicants: TANAKA KIKINZOKU KOGYO K.K., TOKUSHIMA UNIVERSITY
    Inventors: Michimasa OKUBO, Kenji GOTO, Kunihiro TANAKA, Kojiro SHIRAISHI, Kunihiro SHIMA, Yuya KATO, Kenichi HAMADA, Eiichi HONDA, Emi TAKEGAWA
  • Publication number: 20220115412
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 14, 2022
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Patent number: 11296121
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 5, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20220042140
    Abstract: The present invention relates to a medical Au—Pt—Pd alloy including Au, Pt, Pd, and inevitable impurities. The Au—Pt—Pd alloy has an alloy composition inside a polygon (A1-A2-A3-A4) surrounded by straight lines connected at point A1 (Au: 53 atom %, Pt: 4 atom %, and Pd: 43 atom %), point A2 (Au: 70 atom %, Pt: 4 atom %, and Pd: 26 atom %), point A3 (Au: 69.9 atom %, Pt: 30 atom %, and Pd: 0.1 atom %), and point A4 (Au: 49.9 atom %, Pt: 50 atom %, and Pd: 0.1 atom %) in a Au—Pt—Pd ternary state diagram. In a metal structure of the alloy, at least one of a Au-rich phase and a Pt-rich phase is distributed, and the total of the area ratio of the Au-rich phase and the area ratio of the Pt-rich phase is 1.5% or more and 25.4% or less.
    Type: Application
    Filed: September 24, 2020
    Publication date: February 10, 2022
    Applicants: TANAKA KIKINZOKU KOGYO K.K., TOKUSHIMA UNIVERSITY
    Inventors: Michimasa OKUBO, Kenji GOTO, Kunihiro TANAKA, Kojiro SHIRAISHI, Kunihiro SHIMA, Yuya KATO, Kenichi HAMADA, Eiichi HONDA, Emi TAKEGAWA
  • Publication number: 20210242346
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Application
    Filed: February 10, 2021
    Publication date: August 5, 2021
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20210091210
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 25, 2021
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Patent number: 10937897
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: March 2, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10930792
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: February 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20200176606
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 4, 2020
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Patent number: 10559695
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: February 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10326025
    Abstract: To provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability and a manufacturing method of the semiconductor device with high mass productivity. The summary is that an inverted-staggered (bottom-gate) thin film transistor is included in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, a channel protective layer is provided in a region that overlaps a channel formation region of the semiconductor layer, and a buffer layer is provided between the semiconductor layer and source and drain electrodes. An ohmic contact is formed by intentionally providing the buffer layer having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrodes.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 18, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20190157461
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 23, 2019
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Patent number: 9917197
    Abstract: An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: March 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takafumi Mizoguchi, Kojiro Shiraishi, Masashi Tsubuku
  • Patent number: 9859441
    Abstract: In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: January 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20170323957
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20170236943
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Patent number: 9666719
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: May 30, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20170033228
    Abstract: In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 2, 2017
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI