Patents by Inventor Kojiro Shiraishi

Kojiro Shiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8030663
    Abstract: A semiconductor device including thin film transistors having high electrical properties and reliability is proposed. Further, a method for manufacturing the semiconductor devices with mass productivity is proposed. The semiconductor device includes a thin film transistor which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, a source electrode layer and a drain electrode layer over the gate insulating layer, a buffer layer over the source electrode layer and the drain electrode layer, and a semiconductor layer over the buffer layer. A part of the semiconductor layer overlapping with the gate electrode layer is over and in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc. The buffer layer contains a metal oxide having n-type conductivity.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: October 4, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20110115763
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Application
    Filed: January 25, 2011
    Publication date: May 19, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Patent number: 7732241
    Abstract: An object is to provide a microstructure in which shear stress of a structural layer is increased, a manufacturing method thereof, and a microelectromechanical system. A sacrificial layer is formed over a substrate. A metal film is formed over the sacrificial layer. The metal film is irradiated with a laser beam. Needle-like crystals of the metal film are reduced or eliminated. The metal film is etched and processed into a predetermined shape to form a metal layer. Then, the sacrificial layer is removed. Accordingly, a microelectromechanical system which is excellent in reliability and in which a resistance property to breakage of a movable portion of the microstructure is improved can be provided.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: June 8, 2010
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Mayumi Yamaguchi, Konami Izumi, Kojiro Shiraishi
  • Publication number: 20100032666
    Abstract: A semiconductor device including thin film transistors having high electrical properties and reliability is proposed. Further, a method for manufacturing the semiconductor devices with mass productivity is proposed. The semiconductor device includes a thin film transistor which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, a source electrode layer and a drain electrode layer over the gate insulating layer, a buffer layer over the source electrode layer and the drain electrode layer, and a semiconductor layer over the buffer layer. A part of the semiconductor layer overlapping with the gate electrode layer is over and in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc. The buffer layer contains a metal oxide having n-type conductivity.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 11, 2010
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20100032665
    Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 11, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20100032668
    Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. A metal oxide layer having higher carrier concentration than the semiconductor layer is provided intentionally as the buffer layer between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 11, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20100032667
    Abstract: One of the objects of the present invention is to provide a thin film transistor using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn), in which the contact resistance between the oxide semiconductor layer and a source and drain electrodes is reduced, and to provide a method for manufacturing the thin film transistor. An ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the IGZO semiconductor layer and the source and drain electrode layers.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 11, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20100025675
    Abstract: In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 4, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20100025677
    Abstract: To provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability and a manufacturing method of the semiconductor device with high mass productivity. The summary is that an inverted-staggered (bottom-gate) thin film transistor is included in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, a channel protective layer is provided in a region that overlaps a channel formation region of the semiconductor layer, and a buffer layer is provided between the semiconductor layer and source and drain electrodes. An ohmic contact is formed by intentionally providing the buffer layer having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrodes.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 4, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20100025679
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 4, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20100025676
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 4, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20100025678
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 4, 2010
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20070238213
    Abstract: An object is to provide a microstructure in which shear stress of a structural layer is increased, a manufacturing method thereof, and a microelectromechanical system. A sacrificial layer is formed over a substrate. A metal film is formed over the sacrificial layer. The metal film is irradiated with a laser beam. Needle-like crystals of the metal film are reduced or eliminated. The metal film is etched and processed into a predetermined shape to form a metal layer. Then, the sacrificial layer is removed. Accordingly, a microelectromechanical system which is excellent in reliability and in which a resistance property to breakage of a movable portion of the microstructure is improved can be provided.
    Type: Application
    Filed: November 22, 2006
    Publication date: October 11, 2007
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mayumi YAMAGUCHI, Konami IZUMI, Kojiro SHIRAISHI