Patents by Inventor Kojiro Tanaka

Kojiro Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934072
    Abstract: According to one embodiment, a liquid crystal device includes a first liquid crystal cell and a second liquid crystal cell. The first liquid crystal cell and the second liquid crystal cell each include a first strip electrode, a second strip electrode, a third strip electrode and a fourth strip electrode. The extension direction of the first strip electrode and the second strip electrode in the first liquid crystal cell is different from the extension direction of the first strip electrode and the second strip electrode in the second liquid crystal cell. The extension direction of the first strip electrode and the second strip electrode intersects with the extension direction of the third strip electrode and the fourth strip electrode at an angle other than 90°.
    Type: Grant
    Filed: September 12, 2023
    Date of Patent: March 19, 2024
    Assignee: Japan Display Inc.
    Inventors: Kojiro Ikeda, Takeo Koito, Koichi Nagao, Shinichiro Tanaka
  • Patent number: 8430437
    Abstract: A crash can is made of aluminum-alloy casting and provided between a side frame extending in a vehicle longitudinal direction at a side portion of a vehicle and an end portion of a bumper reinforcement extending in a vehicle width direction. The crash can comprises a hollow tube portion extending in the vehicle longitudinal direction and having a cross-shaped section. At least one of an outwardly-projecting corner portion and an inwardly-projecting corner portion of the tube portion is formed by a groove such that a thickness thereof is thinner than that of the other portion of the tube portion. Accordingly, an impact which a vehicle body or a passenger may receive in a vehicle collision can be reduced by the crash can.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: April 30, 2013
    Assignee: Mazda Motor Corporation
    Inventors: Motoyasu Asakawa, Katsuya Nishiguchi, Takahiro Kimura, Nobuyuki Oda, Kojiro Tanaka
  • Publication number: 20120307368
    Abstract: An optical element is provided capable of reducing reflectance at whole bands of visible light. The optical element is characterized in that one of a plurality of concave sections or a plurality of convex sections are arranged on a surface at intervals smaller than a wavelength of visible light, and other not-being-arranged of the plurality of concave sections or the plurality of convex sections are each formed in each of the one arranged of the plurality of concave sections or the plurality of convex sections. A ratio of a lateral cross-sectional area of the optical element itself in a transverse plane taken along a horizontal surface may continuously increase from an upper surface toward a lower surface of the optical element according to a depth between the upper surface and the lower surface.
    Type: Application
    Filed: February 18, 2011
    Publication date: December 6, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Kojiro Tanaka, Shinya Abe, Keiichi Wakayama
  • Publication number: 20120205927
    Abstract: A crash can is made of aluminum-alloy casting and provided between a side frame extending in a vehicle longitudinal direction at a side portion of a vehicle and an end portion of a bumper reinforcement extending in a vehicle width direction. The crash can comprises a hollow tube portion extending in the vehicle longitudinal direction and having a cross-shaped section. At least one of an outwardly-projecting corner portion and an inwardly-projecting corner portion of the tube portion is formed by a groove such that a thickness thereof is thinner than that of the other portion of the tube portion. Accordingly, an impact which a vehicle body or a passenger may receive in a vehicle collision can be reduced by the crash can.
    Type: Application
    Filed: January 13, 2012
    Publication date: August 16, 2012
    Applicant: MAZDA MOTOR CORPORATION
    Inventors: Motoyasu Asakawa, Katsuya Nishiguchi, Takahiro Kimura, Nobuyuki Oda, Kojiro Tanaka
  • Publication number: 20060263773
    Abstract: To be able to easily and rapidly remove free ATP, extract ATP from trapped microorganisms and measure extracted ATP, that loses less microorganisms in a sample, that does not require skill and that can measure the microorganisms in the sample stably and high-sensitively. A flocculant 3 is kept sucked beforehand in a first syringe 2. Then, a liquid sample LS is sucked and agitated. Then, a first filter case 5 and a second filter case 6 are attached immediately to a leading end. Then, this mixture liquid 15 is filtered. Then, only the second filter case 6 is detached and a washing liquid 8 is kept sucked by a second syringe 7 so as to wash the second filter case 6. Next, a bacteriolytic agent 9 is filled in the second filter case 6 and reacted for about 30 seconds. Then, a reacted liquid 16 is pushed out to a measuring tube 10. Then, a luminous reagent (11a+11b) that is prepared beforehand is added. Thereafter, an adapter 12 is attached. Then, it is agitated lightly.
    Type: Application
    Filed: November 30, 2004
    Publication date: November 23, 2006
    Inventor: Kojiro Tanaka
  • Publication number: 20040063869
    Abstract: An isocyanate group-containing hot melt urethane prepolymer, a morpholine ether-based crosslinking catalyst, and at least one sulfur atom-containing organic acid selected from the group consisting of sulfonic acids and sulfinic acids are used as essential components. The urethane prepolymer is a compound having an isocyanate group capable of reacting with moisture in the air or a substrate to be coated to form a crosslinked structure in the molecule. The morpholine ether-based crosslinking catalyst contributes to the moisture-crosslinking reactivity at room temperature. The sulfur atom-containing organic acid contributes to an improvement in thermal stability during melting.
    Type: Application
    Filed: September 24, 2003
    Publication date: April 1, 2004
    Applicant: DAINIPPON INK AND CHEMICALS, INC.
    Inventors: Yukihiko Minamida, Masayoshi Imanaka, Kojiro Tanaka
  • Patent number: 4943943
    Abstract: The present invention provides a read-out circuit for a nonvolatile memory which is capable of extracting a widely-fluctuating output voltage, even when the threshold value of the nonvolatile memory changes only a little.
    Type: Grant
    Filed: July 24, 1984
    Date of Patent: July 24, 1990
    Inventors: Yutaka Hayashi, Yoshikazu Kojima, Masaaki Kamiya, Kojiro Tanaka
  • Patent number: 4821236
    Abstract: A floating gate type semiconductor non-volatile memory injects carriers from a carrier supply region to a floating gate by a phenomenon called "punch-through" injection in which a space charge region is formed in a semiconductor substrate between the carrier supply region and a carrier injection region so as to accelerate the carriers and inject them into the floating gate without forwardly biasing the carrier injection region or the substrate.
    Type: Grant
    Filed: February 9, 1987
    Date of Patent: April 11, 1989
    Assignees: Kogyo Gizyutsuin, Seiko Instruments & Electronics Ltd.
    Inventors: Yutaka Hayashi, Yoshikazu Kojima, Masaaki Kamiya, Kojiro Tanaka
  • Patent number: 4639755
    Abstract: A thermosensitive semiconductor device has a semiconductor substrate of one conductivity type which is used as the common collector of at least two Darlington-connected transistors. The base of the first stage transistor is connected to the common collector to form a first terminal and the emitter of the final stage transistor forms a second terminal. A constant current source is connected between the first and second terminals. To reduce deviations in the temperature response, a second collector region can be used and which can extend to a depth deeper than the depth of the emitter of the final stage transistor to absorb some of the carriers injected by the emitter.
    Type: Grant
    Filed: August 31, 1982
    Date of Patent: January 27, 1987
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventors: Masayuki Namiki, Masaaki Kamiya, Yoshikazu Kojima, Kojiro Tanaka
  • Patent number: 4616340
    Abstract: In the non-volatile semiconductor memory of present invention, a select gate and a floating gate are formed on the surface portion of the substrate between a source region and the drain region also acting as a control gate through a gate oxide film. A part of a channel current is injected into the floating gate at the surface portion under the edge of the floating gate covered by the select gate.
    Type: Grant
    Filed: September 30, 1982
    Date of Patent: October 7, 1986
    Assignees: Agency of Industrial Science & Technology, Kabushiki Kaisha Daini Seikosha
    Inventors: Yutaka Hayashi, Yoshikazu Kojima, Masaaki Kamiya, Kojiro Tanaka
  • Patent number: 4398833
    Abstract: An electronic timepiece including a time-base signal source having a quartz vibrator operating at a frequency of 1 MHz or higher, and a multi-stage divider. At least one stage of the divider is comprised of a static induction transistor logic inverter (SITL inverter), which includes a static induction transistor (SIT) and a bipolar load transistor, operating at a bias voltage of or less than 0.5 volts. The time-base signal source may comprise an oscillator circuit which also includes a static induction transistor.
    Type: Grant
    Filed: August 8, 1980
    Date of Patent: August 16, 1983
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventor: Kojiro Tanaka
  • Patent number: 4395139
    Abstract: A temperature detecting device comprises a semiconductor diode temperature sensor having a resistance characteristic which varies with variations in temperature, and a constant current circuit connected in series. A power source is connected in parallel with the series circuit and connected in parallel with a constant voltage circuit. A resistance ladder circuit is connected between an output terminal of the constant voltage circuit and one terminal of the power source, and an output terminal of the resistance ladder circuit is connected to a first input terminal of a differential amplifier. A second input terminal of the differential amplifier is connected to a connection point of the semiconductor diode and the constant current circuit.
    Type: Grant
    Filed: February 20, 1981
    Date of Patent: July 26, 1983
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventors: Masayuki Namiki, Masaaki Kamiya, Yoshikazu Kojima, Kojiro Tanaka
  • Patent number: 4374332
    Abstract: Within a semiconductor device having two sets of CMOS inverters, the two sets of CMOS inverters are electrically connected in series to a power source for supplying electric power to the semiconductor device. The two sets of CMOS inverters are formed in an oscillating circuit for producing a time base signal and a frequency dividing circuit, respectively. Device operating current and power consumption are accordingly reduced.
    Type: Grant
    Filed: September 16, 1980
    Date of Patent: February 15, 1983
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventors: Nobuo Inami, Kojiro Tanaka
  • Patent number: 4329700
    Abstract: A semiconductor inverter comprised of a pair of junction field effect transistors. A first of the junction field effect transistors is a lateral transistor, and a second of the junction field effect transistors is a vertical transistor. The two junction field transistors have respective channels of opposite conductivity type.
    Type: Grant
    Filed: March 4, 1980
    Date of Patent: May 11, 1982
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventor: Kojiro Tanaka
  • Patent number: 4293782
    Abstract: A voltage detecting circuit, for example for detecting the approaching exhaustion of the battery of a timepiece, hand-held calculator or other small electronic device uses a MOS transistor, the operating point of which in detecting the predetermined voltage is selected as the point at which the ratio of the current to the conductive constant of the MOS transistor is above 0.1. The temperature compensation thereby achieved is good enough that the measured value almost coincides with the design value without the need of using a variable resistor.
    Type: Grant
    Filed: January 28, 1977
    Date of Patent: October 6, 1981
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventors: Kojiro Tanaka, Shozo Ochiai, Hideki Noda
  • Patent number: 4163360
    Abstract: An event timer device having a plurality of memory counters each for memorizing the duration of a respective event. A selecting circuit selects one of the memory counters corresponding to a selected event having a predetermined duration for operating the selected memory counter to count down the memorized duration of the selected event. A display displays the remaining time of the selected event. The event counter further includes an alarm for generating an alarm signal at the end of the selected event.
    Type: Grant
    Filed: July 31, 1978
    Date of Patent: August 7, 1979
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventors: Kojiro Tanaka, Kazuhiro Yoda
  • Patent number: 4138613
    Abstract: A switching circuit including a flip-flop which receives a switching signal that sets the flip-flop and which receives a reset signal which resets the flip-flop. A latching circuit, responsive to a clock signal, is connected to receive an output signal of the flip-flop for developing a latching circuit output signal corresponding to the output signal of the flip-flop at a time the clock signal is applied thereto. A reset signal and a clock signal developed repetitively and out of phase are respectively applied to the flip-flop and the latching circuit so that the latching circuit output signal can change only after the flip-flop has been reset.
    Type: Grant
    Filed: August 9, 1977
    Date of Patent: February 6, 1979
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventor: Kojiro Tanaka
  • Patent number: 4102122
    Abstract: An electronic watch including a time counter, a day counter and a month counter for developing counts respectively representing time of the day, day of the month, and the month. The day counter is responsive to a control signal for limiting a maximum count of the day counter to 28, 29, 30 or 31 days. A control signal circuit develops the control signal and applied the same to the day counter for limiting the maximum count of the day counter to 31 days during a long month, 30 days during a short month, and 28 or 29 days during February. The watch further includes a display responsive to the respective counts of the various counters for displaying time of the day, day of the month, and the month.
    Type: Grant
    Filed: November 4, 1976
    Date of Patent: July 25, 1978
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventor: Kojiro Tanaka
  • Patent number: 4095407
    Abstract: An oscillation and dividing circuit having a level shifter for an electric timepiece comprises an oscillating circuit, a multi-stage dividing circuit for dividing the frequency of the oscillating circuit and a delay circuit. The outputs of the dividing circuit and the delay circuit are connected through a NAND circuit to the base of a P-FET of the level shifter circuit. The output of the oscillating circuit is connected through an inverter to one input terminal of the first stage of the dividing circuit and through a second inverter to the other input terminal. The output of one stage of the dividing circuit is connected as a control circuit to the delay circuit, thereby supplying a square wave control signal even if the oscillating circuit produces a distorted signal. The pulse width of the pulse applied to the level-shifter is hence constant in spite of poor functioning of the oscillating circuit and a high output voltage is attained.
    Type: Grant
    Filed: July 6, 1976
    Date of Patent: June 20, 1978
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventors: Kazuhiro Asano, Kojiro Tanaka
  • Patent number: 4095405
    Abstract: An all electronic watch has an analog minute and hour display comprising two concentric circles of radially disposed LEDs which are energized sequentially in a manner to simulate the movement of the minute and hour hands of a mechanical watch, and a centrally located digital display of date. The circuitry for energizing the LEDs of the analog minute and hour display and the digital date display comprise up-down counters. Amendment of time in a forward direction or in a backward direction is effected by switches actuated by the crown of the watch to feed fast pulses to the counters to operate the counters in a forward direction or in a backward direction as desired. The crown has two operational positions and is rotatable selectively in opposite directions in the manner of a mechanical watch to effect time and date amendment forwardly or backwardly.
    Type: Grant
    Filed: September 23, 1976
    Date of Patent: June 20, 1978
    Assignee: Kabushiki Kaisha Daini Seikosha
    Inventor: Kojiro Tanaka