Patents by Inventor Kok Lim
Kok Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10243576Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.Type: GrantFiled: May 9, 2018Date of Patent: March 26, 2019Assignee: Maxlinear, Inc.Inventors: Eric Fogleman, Sheng Ye, Xuefeng Chen, Kok Lim Chan
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Publication number: 20180262201Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.Type: ApplicationFiled: May 9, 2018Publication date: September 13, 2018Inventors: Eric Fogleman, Sheng Ye, Xuefeng Chen, Kok Lim Chan
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Patent number: 10033412Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.Type: GrantFiled: December 11, 2017Date of Patent: July 24, 2018Assignee: XILINX, INC.Inventors: Siok Wei Lim, Kok Lim Chan, Kee Hian Tan, Hongyuan Zhao, Chin Yang Koay, Yohan Frans, Kun-Yung Chang
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Patent number: 10003347Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.Type: GrantFiled: September 21, 2017Date of Patent: June 19, 2018Assignee: Maxlinear, Inc.Inventors: Eric Fogleman, Sheng Ye, Xuefeng Chen, Kok Lim Chan
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Publication number: 20180102797Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.Type: ApplicationFiled: December 11, 2017Publication date: April 12, 2018Applicant: Xilinx, Inc.Inventors: Siok Wei Lim, Kok Lim Chan, Kee Hian Tan, Hongyuan Zhao, Chin Yang Koay, Yohan Frans, Kun-Yung Chang
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Publication number: 20180041232Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.Type: ApplicationFiled: August 3, 2016Publication date: February 8, 2018Applicant: Xilinx, Inc.Inventors: Siok Wei Lim, Kok Lim Chan, Kee Hian Tan, Hongyuan Zhao, Chin Yang Koay, Yohan Frans, Kun-Yung Chang
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Patent number: 9887710Abstract: A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.Type: GrantFiled: August 3, 2016Date of Patent: February 6, 2018Assignee: XILINX, INC.Inventors: Siok Wei Lim, Kok Lim Chan, Kee Hian Tan, Hongyuan Zhao, Chin Yang Koay, Yohan Frans, Kun-Yung Chang
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Publication number: 20180013442Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.Type: ApplicationFiled: September 21, 2017Publication date: January 11, 2018Inventors: Eric Fogleman, Sheng Ye, Xuefeng Chen, Kok Lim Chan
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Patent number: 9853642Abstract: An example output driver includes a plurality of output circuits coupled in parallel between a first voltage supply node and a second voltage supply node. Each of the plurality of output circuits includes a differential input that is coupled to receive a logic signal of a plurality of logic signals and a differential output that is coupled to a common output node. The output driver further includes voltage regulator(s), coupled to the voltage supply node(s), and a current compensation circuit. The current compensation circuit includes a switch coupled in series with a current source, where the switch and the current source are coupled between the first voltage supply node and the second voltage supply node. An event detector is coupled to the switch to supply an enable signal and to control state of the enable signal based on presence of a pattern in the plurality of logic signals.Type: GrantFiled: August 11, 2016Date of Patent: December 26, 2017Assignee: XILINX, INC.Inventors: Kee Hian Tan, Kok Lim Chan, Siok Wei Lim
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Publication number: 20170346500Abstract: A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.Type: ApplicationFiled: August 11, 2017Publication date: November 30, 2017Inventors: Xuefeng Chen, Kok Lim Chan, Eric Fogleman, Sheng Ye
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Patent number: 9800253Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.Type: GrantFiled: August 8, 2016Date of Patent: October 24, 2017Assignee: Maxlinear, Inc.Inventors: Eric Fogleman, Sheng Ye, Xuefeng Chen, Kok Lim Chan
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Publication number: 20170134032Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.Type: ApplicationFiled: August 8, 2016Publication date: May 11, 2017Inventors: Eric Fogleman, Sheng Ye, Xuefeng Chen, Kok Lim Chan
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Patent number: 9537503Abstract: Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information. The plurality of signal state circuits, plurality of signal adjustment circuits, and the timing control circuit may be arranged to generate one or more control signals for controlling an analog-to-digital converter (ADC) during the analog-to-digital conversions.Type: GrantFiled: May 10, 2016Date of Patent: January 3, 2017Assignee: MAXLINEAR, INC.Inventors: Xuefeng Chen, Kok Lim Chan, Eric Fogleman, Sheng Ye
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Publication number: 20160322985Abstract: Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information.Type: ApplicationFiled: May 10, 2016Publication date: November 3, 2016Inventors: Xuefeng Chen, Kok Lim Chan, Eric Fogleman, Sheng Ye
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Patent number: 9413378Abstract: Methods and systems are provided for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) that utilize preemptive bit setting decisions. In particular, such SAR ADC may be operable to, when a failure to determine a valid output decision for each comparison step occurs, set one or more remaining bits, up to but not including one or more overlapping redundant bits in a code word corresponding to the comparison step, to a particular value. The value may be derived from a value of a bit determined in an immediately preceding decision. The failure may be determined based on dynamic and/or adaptive criteria. The criteria may be set, e.g., so as to guarantee that a magnitude of a difference between an analog input voltage to the SAR ADC and analog output voltage of a digital-to-analog converter (DAC) used therein is within overlapping ranges of voltages corresponding to the overlapping redundant bits.Type: GrantFiled: September 2, 2015Date of Patent: August 9, 2016Assignee: Maxlinear, Inc.Inventors: Eric Fogleman, Sheng Ye, Xuefeng Chen, Kok Lim Chan
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Patent number: 9337859Abstract: Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels.Type: GrantFiled: July 29, 2015Date of Patent: May 10, 2016Assignee: MAXLINEAR, INC.Inventors: Xuefeng Chen, Kok Lim Chan, Eric Fogleman, Sheng Ye
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Publication number: 20160006450Abstract: Methods and systems are provided for controlling signal processing outputs. In signal processing circuitry, searching through a plurality of quantization levels for a quantization level that matches an analog input, and when the search fails within a particular amount of time, adjusting at least a portion of an output of the signal processing circuitry. The adjusting comprises setting the at least portion of the output to a predefined value. Setting the output, or portions thereof, may comprise selecting between output of a normal processing path and output of a code generation path configured for handling search failures. Timing information may be generated for use in controlling generating of the output of the signal processing circuitry. The timing information may be used in measuring per-cycle operation time during the search through the plurality of quantization levels.Type: ApplicationFiled: July 29, 2015Publication date: January 7, 2016Inventors: Xuefeng Chen, Kok Lim Chan, Eric Fogleman, Sheng Ye
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Publication number: 20150381196Abstract: Methods and systems are provided for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) that utilize preemptive bit setting decisions. In particular, such SAR ADC may be operable to, when a failure to determine a valid output decision for each comparison step occurs, set one or more remaining bits, up to but not including one or more overlapping redundant bits in a code word corresponding to the comparison step, to a particular value. The value may be derived from a value of a bit determined in an immediately preceding decision. The failure may be determined based on dynamic and/or adaptive criteria. The criteria may be set, e.g., so as to guarantee that a magnitude of a difference between an analog input voltage to the SAR ADC and analog output voltage of a digital-to-analog converter (DAC) used therein is within overlapping ranges of voltages corresponding to the overlapping redundant bits.Type: ApplicationFiled: September 2, 2015Publication date: December 31, 2015Inventors: Eric Fogleman, Sheng Ye, Xuefeng Chen, Kok Lim Chan
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Patent number: 9136859Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.Type: GrantFiled: December 30, 2014Date of Patent: September 15, 2015Assignee: MAXLINEAR, INC.Inventors: Eric Fogleman, Sheng Ye, Xuefeng Chen, Kok Lim Chan
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Patent number: 9124291Abstract: A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.Type: GrantFiled: July 18, 2013Date of Patent: September 1, 2015Assignee: MAXLINEAR, INC.Inventors: Xuefeng Chen, Kok Lim Chan, Eric Fogleman, Sheng Ye