Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Abstract: An analogue to digital converter includes a first input connection to receive a first part of the analogue input signal, a second input connection to receive a second part of the analogue input signal, a first and second plurality of capacitors, each capacitor of the first plurality of capacitors forms a capacitor pair with a corresponding capacitor in the second plurality of capacitors During a sampling period, the first input connection couples the first part of the analogue input signal to a first contact of each capacitor of the first plurality of capacitors and the second input connection couples the second part of the analogue input signal to a first contact of each capacitor of the second plurality of capacitors. Further, a switching array couples a second contact of each capacitor of the first and second plurality of capacitors to a common mode voltage to determine a first bit of a digital output signal.

Abstract: According to embodiments of the present invention, an analog-to-digital converter is provided. The analog-to-digital converter includes an input configured to receive an input signal, a feed-forward path connected to the input configured to feed forward the input signal, a processing path including a loop filter, wherein the loop filter includes at least one local feedback path configured to feed back an output signal of the loop filter to an input of the loop filter, a first combiner configured to combine the input signal fed forward by the feed-forward path with an output of the processing path, a quantizer configured to generate an output signal of the converter, a feed-back path configured to feed back the output signal, and a second combiner wherein the processing path is connected to the second combiner and the second combiner is configured to combine the input signal with the fed back output signal of the converter and supply the result of the combination to the processing path.

Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

Abstract: A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.

Abstract: An analogue to digital converter comprises a first input connection to receive a first part of the analogue input signal; a second input connection to receive a second part of the analogue input signal; a first and second plurality of capacitors, each capacitor of the first plurality of capacitors forms a capacitor pair with a corresponding capacitor in the second plurality of capacitors; wherein, during a sampling period, the first input connection couples the first part of the analogue input signal to a first contact of each capacitor of the first plurality of capacitors, the second input connection couples the second part of the analogue input signal to a first contact of each capacitor of the second plurality of capacitors, and a switching array couples a second contact of each capacitor of the first and second plurality of capacitors to a common mode voltage to determine a first bit of the digital output signal.

Abstract: According to embodiments of the present invention, a micro-sensory tip for use in blood vessels is provided. The micro-sensory tip includes: a force transmission element; at least three force detecting sensors coupled to the force transmission element, each of the at least three force detecting sensors responsive to force applied on the force transmission element, wherein each of the at least three force detecting sensors produces an output representing at least one force component of a three-dimensional Cartesian co-ordinate system, of the force experienced by the force transmission element, such that the outputs of the at least three force detecting sensors can cover the space of the three-dimensional Cartesian co-ordinate system; and an active element arrangement coupled to the at least three force detecting sensors, the active element arrangement configured to process the output from the at least three force detecting sensors.

Abstract: According to embodiments of the present invention, an implantable device for detecting variation in fluid flow rate is provided. The implantable device includes: a substrate having an active element arrangement; a sensor arrangement having a first portion that is mechanically secured and a second portion that is freely deflectable, the sensor arrangement in electrical communication with the active element arrangement, wherein the active element arrangement is configured to detect changes in deformation of the sensor arrangement and produce an output in response to the detected changes; and at least one inductive element mechanically coupled to the substrate and in electrical communication with the active element arrangement, wherein the inductive element is adapted to power the active element arrangement through inductive coupling to an excitation source, and wherein the inductive element is adapted to transmit the output associated with the detected changes in the sensor.

Abstract: In one embodiment, the invention includes a controller that interrupts a CPU based on a counter that uses a decrement step which may increase as high priority data packets are received by the controller.

Abstract: A circuit arrangement is provided.

Abstract: In one embodiment, the invention includes a controller that interrupts a CPU based on a counter that uses a decrement step which may increase as high priority data packets are received by the controller.

Abstract: A method and apparatus to support communication between components in different clock domains having a rational clock frequency ratio of N/D. In one embodiment, a combination of integer phase generators are employed to produce phase control signals during an overall cycle having N phases, wherein the overall cycle is a combination of primary cycles having D phases and an adjustment cycle having R phases, wherein R is the remainder of N/D. For clock frequency ratios of less than 2:1, a combination of 2:1 and 1:1 phase generators are employed. Clocking signals are generated by phase generator logic to provide timing control between communicating components in the different clock domains. In one embodiment, the phase generator logic is implemented in a programmable phase generator.

Abstract: A food processor includes a drive unit, a food processing tool driven rotatably by the drive unit, a rotary support, and a transmission device. The transmission device includes a first transmission unit driven rotatably by the drive unit and defining a first drive axis, a second transmission unit driving rotation of the rotary support and defining a second drive axis, and a coupling member that couples the first transmission unit to the second transmission unit. The coupling member permits movement of the first transmission unit relative to the second transmission unit from a first position, where the first drive axis is aligned with the second drive axis, to a second position, where the first drive axis forms an angle with the second drive axis. The coupling member enables transmission of drive power from the drive unit to the rotary support when the first transmission unit is at the first position.

Abstract: The present invention provides a theft-deterrent mechanism and method that minimizes or eliminates the loss of electronic devices during transportation and sales due to theft, and a retail packaging that comprises the theft-mechanism.

Abstract: A social marketing network (5) for marketing digital content (6, 7, 8) the network (5) comprising: a first shop (10) to sell particular digital content (6, 7, 8); a plurality of second shops (15, 20, 25) to sell the particular digital content (6, 7, 8), the second shops (15, 20, 25) being affiliated to the first shop (10) and classified in levels relative to the first shop (10); wherein the particular digital content (6, 7, 8) is available for re-sale at any shop (10, 15, 20, 25) within the social marketing network (5) and the revenue earned by the first shop (10) is determined by a predetermined commission scale based on the level of the shop (10, 15, 20, 25) which sold the particular digital content (6, 7, 8) relative to the first shop (10).

Abstract: A food processor includes a drive unit, a food processing tool driven rotatably by the drive unit, a rotary support, and a transmission device. The transmission device includes a first transmission unit driven rotatably by the drive unit and defining a first drive axis, a second transmission unit driving rotation of the rotary support and defining a second drive axis, and a coupling member that couples the first transmission unit to the second transmission unit. The coupling member permits movement of the first transmission unit relative to the second transmission unit from a first position, where the first drive axis is aligned with the second drive axis, to a second position, where the first drive axis forms an angle with the second drive axis. The coupling member enables transmission of drive power from the drive unit to the rotary support when the first transmission unit is at the first position.

Abstract: A method and apparatus to support communication between components in different clock domains having a rational clock frequency ratio of N/D. In one embodiment, a combination of integer phase generators are employed to produce phase control signals during an overall cycle having N phases, wherein the overall cycle is a combination of primary cycles having D phases and an adjustment cycle having R phases, wherein R is the remainder of N/D. For clock frequency ratios of less than 2:1, a combination of 2:1 and 1:1 phase generators are employed. Clocking signals are generated by phase generator logic to provide timing control between communicating components in the different clock domains. In one embodiment, the phase generator logic is implemented in a programmable phase generator.

Abstract: A computer implemented method animates a 3D physical object by first acquiring a 3D graphics model of the object. The model is edited with graphics authoring tools to reflect a desired appearance of the object. The edited model is rendered as an image considering a user location and a location of a virtual light. Then, intensity values of the image are corrected according to an orientation of a surface of the object and a radiance at the surface. The 3D physical object can finally be illuminated with the corrected image to give the 3D physical object the desired appearance under the virtual light when viewed from the user location.

Abstract: An apparatus comprising a voltage divider, a counter and a comparison circuit. The voltage divider is coupled to a first reference and includes a reference impedance and an adjustable impedance circuit coupled to the reference impedance circuit at a first node. The adjustable impedance circuit includes inputs to adjust the impedance according to a weighted coding pattern. The counter includes at least one input to cause the counter to count and change counter outputs in accordance with a weighted coding pattern that includes a pseudo-thermometer code. The counter outputs are coupled to the inputs of the adjustable impedance circuit. The comparison circuit is coupled to the first node and causes the counter to count in accordance with an outcome of a comparison between the first node and a second reference.