Abstract: A core substrate-less electronic device is fabricated by using an electronic device substrate 10. The electronic device substrate 10 a metal core substrate 11, and an external connection wiring layer 100 provided on the metal core substrate 11, and an electronic parts-mounting layer 110 provided on the external connection wiring layer 100. The external connection wiring layer 100 has a first plating film 103 as an external connection terminal, and a PSR film 101 as an electrical insulating material. The electronic parts-mounting layer 110 has a conductive film 113 as an internal conductor pattern and a PSR film 111 as an electrical insulating material. A surface of the conductive film 113 is in a same plane as a surface of the PSR film 111.

Abstract: A lead frame of the present invention includes a plurality of tie bars including tie bars each having deformable portions that protect opposite outside frames from deformation. The outside frames each are formed with positioning holes. Element loading portions to be loaded with semiconductor elements are connected to the outside frames by such tie bars. The lead frame is therefore free from deformation during lead forming while promoting the miniaturization of the semiconductor devices.

Abstract: An electronic device substrate is formed of a thin-plate reinforcing substrate; an external connection wiring layer stacked on the reinforcing substrate, and comprising an electrical insulation provided on the reinforcing substrate, an opening formed in the electrical insulation, a first conductor pattern and a via-hole conductor provided in the opening and formed integrally with each other; and a second conductor pattern formed on the opposite side of the electrical insulation to the reinforcing substrate, and at least partially electrically connected to the via-hole conductor.

Abstract: In an optical semiconductor integrated circuit device using a lead frame, a transparent epoxy resin composition for molding an optical semiconductor contains (A) an epoxy resin; (B) a curing agent; (C) a thiol; and (D) an amine-based curing catalyst represented by following Chemical Formula 1: R1: a hydrogen atom (—H), an alkyl group, or a phenyl group R2: an alkyl group (—CH3, —C2H5, —C3H7)

Abstract: A recess for fully receiving an electronic component and a window opened from the bottom of the recess to the bottom surface of a metal substrate are formed in the metal substrate. A wiring board is bonded to the underside of the metal substrate, and the electronic component is fixed to the bottom of the recess. Input and output terminals of the electronic component are connected to electrode pads of the wiring board exposed within the window using wire bonding. A metal lid is bonded to the top surface of the metal substrate to close the opening of the recess. Electromagnetic waves generated by the electronic component are confined to the electronic device because the electronic device is surrounded by the metal substrate, the metal lid, and a ground electrode disposed on the wiring board. Heat dissipation performance is assured because the electronic component is connected to the metal substrate.

Abstract: An electronic device substrate is provided with a thin-plate core substrate; a metal electrode provided on the core substrate and electrically connected to an electrode of an electronic component to be packaged thereon; and an electrical insulation layer on which is mounted the electronic component, and which is provided to surround the metal electrode.

Abstract: An optical semiconductor device includes: an insulating base; and a lead structure which further includes: a flange supported on a first surface of the insulating base; at least a first type lead supported by the insulating base; at least an island for mounting at least an optical semiconductor element thereon, which is electrically connected to the at least first type lead; and at least a connection part extending between the at least island and the flange. The flange, the at least connection part, and the at least island comprise a single united part of the lead structure. The flange, the at least connection part, the at least island, and the at least first type lead comprise a same conductive material.

Abstract: A recess for fully receiving an electronic component and a window opened from the bottom of the recess to the bottom surface of a metal substrate are formed in the metal substrate. A wiring board is bonded to the underside of the metal substrate, and the electronic component is fixed to the bottom of the recess. Input and output terminals of the electronic component are connected to electrode pads of the wiring board exposed within the window using wire bonding. A metal lid is bonded to the top surface of the metal substrate to close the opening of the recess. Electromagnetic waves generated by the electronic component are confined to the electronic device because the electronic device is surrounded by the metal substrate, the metal lid, and a ground electrode disposed on the wiring board. Heat dissipation performance is assured because the electronic component is connected to the metal substrate.

Abstract: An optical semiconductor device includes: an insulating base; and a lead structure which further includes: a flange supported on a first surface of the insulating base; at least a first type lead supported by the insulating base; at least an island for mounting at least an optical semiconductor element thereon, which is electrically connected to the at least first type lead; and at least a connection part extending between the at least island and the flange. The flange, the at least connection part, and the at least island comprise a single united part of the lead structure. The flange, the at least connection part, the at least island, and the at least first type lead comprise a same conductive material.

Abstract: An electronic device includes (a) a first wiring substrate including a metal area and formed with a recess reaching the metal area, and (b) a second wiring substrate including a ground electrode formed in an area other than a signal transmission path at the recess and around the recess when coupled to the first wiring substrate, and further including at least one first electronic part mounted thereon. The first and second wiring substrates are coupled directly to each other such that the first electronic part is located in the recess.

Abstract: A multilayered circuit board for a semiconductor chip module includes an underlying board, insulating layers, fixed-potential wiring layers, via holes, and metal layers. The underlying board has a major surface made of a metal material to which a fixed potential is applied. The insulating layers are stacked on the major surface of the underlying board and have wiring layers formed on their surfaces. The fixed-potential wiring layers constitute part of the wiring layers formed on the insulating layers. The via holes are formed below the fixed-potential wiring layers to extend through the insulating layers. The metal layers are filled in the via holes so as to make upper ends be connected to the lower surfaces of the fixed-potential wiring layers. One of the insulating layers in contact with the major surface of the underlying board is formed on the underlying board while the lower end of the metal layer is in contact with the major surface of the underlying board.

Abstract: A first conductive layer is formed on the bottom surface of a substrate, including a bottom section, a step and a side wall, and a light emitting device is mounted on the first conductive layer. A second conductive layer is formed on the step, and is electrically connected to the fight emitting device. The substrate is filled with a translucent resin. A third and fourth conductive layers, which are insulated from each other, are formed on a cap in the form of plate which is attached to an opening of the substrate. A photodetector facing the light emitting device is mounted on the third conductive layer, thereby the light emitting device and the fourth conductive layer are electrically connected with each other. The conductive layers are respectively connected to external electrodes, which are formed on the external surface of the substrate, via through holes formed through the substrate.

Abstract: A compact semiconductor circuitry device capable of providing a high production efficiency and of shortening time required for packaging and a method for manufacturing a same are provided. A terminal supplying tape having a metal thin film member mounted, on a base material film, in a same arrangement pattern as for a chip terminal of a semiconductor chip and in a state in which it can be peeled off, is prepared in advance. The terminal supplying tape and the semiconductor chip are so disposed as to face each other. The metal thin film member of the terminal supplying tape is connected to the chip terminal, with the terminal supplying tape remaining fixed on the base material film. Then, the base material film is peeled off. An underfill is mounted as necessary. A resin molded portion is also mounted.

Abstract: A multilayered wiring structure includes a lower wiring layer, an interlevel insulating layer, a filling layer, an upper wiring layer, and a plated layer. The lower wiring layer is formed on a lead frame through an insulating layer. The interlevel insulating layer is formed on the lower wiring layer to have a via hole at a predetermined region thereof to expose an upper portion of the lower wiring layer. The filling layer is made of a conductive material to fill the via hole. The upper wiring layer is formed on the interlevel insulating layer to have an opening above a portion where the via hole is formed. The plated layer is formed on the upper wiring layer to be connected to the filling layer. A method of manufacturing a multilayered wiring structure is also disclosed.

Abstract: A lead frame of the present invention includes a plurality of tie bars including tie bars each having deformable portions that protect opposite outside frames from deformation. The outside frames each are formed with positioning holes. Element loading portions to be loaded with semiconductor elements are connected to the outside frames by such tie bars. The lead frame is therefore free from deformation during lead forming while promoting the miniaturization of the semiconductor devices.

Abstract: A hybrid integrated circuit includes a metal lead frame, a wiring structure, an integrated circuit chip, and a lead. The wiring structure is comprised of a wiring layer formed on the upper surface of the lead frame through an insulating layer. The integrated circuit chip is arranged on the wiring structure and connected to a predetermined portion of the wiring structure. A terminal is arranged near the lead frame to be insulated and isolated from the lead frame and connected to the predetermined portion of the wiring structure. The insulating layer has an extending connecting portion extending from the wiring structure to be connected to the lead frame. A fixed potential is connected to the integrated circuit chip through the extending connecting portion and the lead frame.

Abstract: A multilayered wiring structure includes a lower wiring layer, an interlevel insulating layer, a filling layer, an upper wiring layer, and a plated layer. The lower wiring layer is formed on a lead frame through an insulating layer. The interlevel insulating layer is formed on the lower wiring layer to have a via hole at a predetermined region thereof to expose an upper portion of the lower wiring layer. The filling layer is made of a conductive material to fill the via hole. The upper wiring layer is formed on the interlevel insulating layer to have an opening above a portion where the via hole is formed. The plated layer is formed on the upper wiring layer to be connected to the filling layer. A method of manufacturing a multilayered wiring structure is also disclosed.

Abstract: A multilayered wiring structure includes a lower wiring layer, an interlevel insulating layer, a filling layer, an upper wiring layer, and a plated layer. The lower wiring layer is formed on a lead frame through an insulating layer. The interlevel insulating layer is formed on the lower wiring layer to have a via hole at a predetermined region thereof to expose an upper portion of the lower wiring layer. The filling layer is made of a conductive material to fill the via hole. The upper wiring layer is formed on the interlevel insulating layer to have an opening above a portion where the via hole is formed. The plated layer is formed on the upper wiring layer to be connected to the filling layer. A method of manufacturing a multilayered wiring structure is also disclosed.