Patents by Inventor Koki Muto
Koki Muto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7585733Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing a semiconductor substrate having first and second element forming regions, the first and second element forming regions divided by an element separating insulation film; forming a first gate insulation film on the semiconductor substrate; forming a predetermined film on the first gate insulation film; forming a protective film on the predetermined film in the first element forming region; forming a second gate insulation film in the second element forming region by deforming the predetermined film into an insulation film using the protective film as a mask; removing the protective film and the remaining predetermined film which is not deformed into the insulated film; and forming gate electrodes on the first and second gate insulation films which are exposed by removing the remaining predetermined film.Type: GrantFiled: January 30, 2006Date of Patent: September 8, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Koki Muto
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Patent number: 7232723Abstract: There is provided a method of fabricating a semiconductor device comprising the steps of applying resist to a polysilicon film formed across the surface of a substrate and forming a plurality of openings in a resist pattern, for determining a spacing between floating gates adjacent to each other, causing the openings of the resist pattern to undergo uniform contraction by use of, for example, deformation due to thermal flow to thereby form other openings, and etching portions of the polysilicon film, in the openings as contracted to thereby form the floating gate on both sides of the respective openings as contracted. With the method described, it becomes possible to reduce the spacing between the floating gates adjacent to each other above the resolution limit of an exposure system, thereby enlarging a floating gate width.Type: GrantFiled: July 27, 2006Date of Patent: June 19, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Koki Muto
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Publication number: 20060263982Abstract: There is provided a method of fabricating a semiconductor device comprising the steps of applying resist to a polysilicon film formed across the surface of a substrate and forming a plurality of openings in a resist pattern, for determining a spacing between floating gates adjacent to each other, causing the openings of the resist pattern to undergo uniform contraction by use of, for example, deformation due to thermal flow to thereby form other openings, and etching portions of the polysilicon film, in the openings as contracted to thereby form the floating gate on both sides of the respective openings as contracted. With the method described, it becomes possible to reduce the spacing between the floating gates adjacent to each other above the resolution limit of an exposure system, thereby enlarging a floating gate width.Type: ApplicationFiled: July 27, 2006Publication date: November 23, 2006Inventor: Koki Muto
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Patent number: 7105407Abstract: There is provided a method of fabricating a semiconductor device comprising the steps of applying resist to a polysilicon film formed across the surface of a substrate and forming a plurality of openings in a resist pattern, for determining a spacing between floating gates adjacent to each other, causing the openings of the resist pattern to undergo uniform contraction by use of, for example, deformation due to thermal flow to thereby form other openings, and etching portions of the polysilicon film, in the openings as contracted to thereby form the floating gate on both sides of the respective openings as contracted. With the method described, it becomes possible to reduce the spacing between the floating gates adjacent to each other above the resolution -limit of an exposure system, thereby enlarging a floating gate width.Type: GrantFiled: December 30, 2003Date of Patent: September 12, 2006Assignee: Oki Electric Industry Co., Ltd.Inventor: Koki Muto
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Publication number: 20060194393Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing a semiconductor substrate having first and second element forming regions, the first and second element forming regions divided by an element separating insulation film; forming a first gate insulation film on the semiconductor substrate; forming a predetermined film on the first gate insulation film; forming a protective film on the predetermined film in the first element forming region; forming a second gate insulation film in the second element forming region by deforming the predetermined film into an insulation film using the protective film as a mask; removing the protective film and the remaining predetermined film which is not deformed into the insulated film; and forming gate electrodes on the first and second gate insulation films which are exposed by removing the remaining predetermined film.Type: ApplicationFiled: January 30, 2006Publication date: August 31, 2006Applicant: Oki Electric Industry Co., Ltd.Inventor: Koki Muto
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Patent number: 6869738Abstract: The main mask pattern of a photomask is corrected by adding serifs of one type (inner or outer) to a pair of mutually adjacent corners in the pattern, and adding a serif of the opposite type (outer or inner) to the edge between the corners. When the photomask is used to create a resist pattern by photolithography in the fabrication of a semiconductor device, the serifs combine to produce an optical proximity correction that reduces corner rounding and increases edge straightness in the resist pattern.Type: GrantFiled: November 27, 2002Date of Patent: March 22, 2005Assignee: Oki Electric Industry Co., Ltd.Inventors: Katsuo Oshima, Koki Muto
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Patent number: 6838643Abstract: An apparatus for baking a semiconductor wafer having a resist pattern thereon includes a baking oven in which the semiconductor wafer is placed and heated, and a first hot plate which is provided in the baking oven to heat an entire bottom surface of the semiconductor wafer. The apparatus also includes a gas supply unit having a gas introducing path, through which the purge gas is introduced into the baking oven, and a gas exhaust path, through which the purge gas is exhausted out of the baking oven. A gas temperature controller controls a temperature of the purge gas in order that the purge gas flowing around a peripheral edge or outer portion of the wafer has a higher temperature than that around the center or inner portion of the wafer.Type: GrantFiled: July 18, 2002Date of Patent: January 4, 2005Assignee: OKI Electric Industry Co., Ltd.Inventors: Shouzou Kobayashi, Takamitsu Furukawa, Keisuke Tanaka, Kouhei Shimoyama, Akira Watanabe, Tadashi Nishimuro, Koki Muto, Azusa Yanagisawa, Katsuo Oshima
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Publication number: 20040229467Abstract: There is provided a method of fabricating a semiconductor device comprising the steps of applying resist to a polysilicon film formed across the surface of a substrate and forming a plurality of openings in a resist pattern, for determining a spacing between floating gates adjacent to each other, causing the openings of the resist pattern to undergo uniform contraction by use of, for example, deformation due to thermal flow to thereby form other openings, and etching portions of the polysilicon film, in the openings as contracted to thereby form the floating gate on both sides of the respective openings as contracted. With the method described, it becomes possible to reduce the spacing between the floating gates adjacent to each other above the resolution -limit of an exposure system, thereby enlarging a floating gate width.Type: ApplicationFiled: December 30, 2003Publication date: November 18, 2004Inventor: Koki Muto
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Patent number: 6656795Abstract: A method of manufacturing a semiconductor memory element is disclosed. The method includes arranging a mask on the upper surface of a semiconductor substrate, using the mask to conduct exposure, forming first, second, and third element-isolation regions on the semiconductor substrate surface, and forming a gate electrode. A resist film is formed on the substrate. On the mask, auxiliary patterns are made at the each central portion of first, second, and third patterns. In the exposure with the mask, first, second, and third resist patterns is formed on the resist film. The resist patterns respectively correspond to the patterns on the mask. The gate electrode extending in the second direction is formed from the upper surface of the second element-isolation region to the upper surface of the third electrode element-isolation region through an area between the second and third element-isolation regions.Type: GrantFiled: December 23, 2002Date of Patent: December 2, 2003Assignee: Oki Electric Industry Co., Ltd.Inventor: Koki Muto
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Publication number: 20030162103Abstract: The main mask pattern of a photomask is corrected by adding serifs of one type (inner or outer) to a pair of mutually adjacent corners in the pattern, and adding a serif of the opposite type (outer or inner) to the edge between the corners. When the photomask is used to create a resist pattern by photolithography in the fabrication of a semiconductor device, the serifs combine to produce an optical proximity correction that reduces corner rounding and increases edge straightness in the resist pattern.Type: ApplicationFiled: November 27, 2002Publication date: August 28, 2003Inventors: Katsuo Oshima, Koki Muto
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Publication number: 20030057198Abstract: An apparatus for baking a semiconductor wafer having a resist pattern thereon, comprising: a baking oven in which the semiconductor wafer is placed and heated; a first hot plate which is provided in the baking oven to heat an entire bottom surface of the semiconductor wafer; a gas supply unit which comprises a gas introducing path, through which the purge gas is introduced into the baking oven, and a gas exhaust path, through which the purge gas is exhausted out of the baking oven; and a gas temperature controller which controls a temperature of the purge gas in order that the purge gas flowing around a peripheral edge or outer portion of the wafer has a higher temperature than that around the center or inner portion of the wafer.Type: ApplicationFiled: July 18, 2002Publication date: March 27, 2003Inventors: Shouzou Kobayashi, Takamitsu Furukawa, Keisuke Tanaka, Kouhei Shimoyama, Akira Watanabe, Tadashi Nishimuro, Koki Muto, Azusa Yanagisawa, Katsuo Oshima
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Patent number: 6455438Abstract: According to the present invention, a semiconductor device is fabricated by the following processes. First, a film to be etched is formed on a semiconductor substrate. On the film to be etched is formed a resist film. Then, a first pattern group including first patterns having a first size and a second pattern group including second patterns arranged outside of the first pattern group are formed by exposure. The resist film is then developed to form openings in the resist film so that the resultant openings correspond to the first and second patterns, respectively. The openings are then made smaller by annealing the resist film. The aforementioned processes enables openings having substantially the same shape to be formed in the film to be etched.Type: GrantFiled: September 15, 2000Date of Patent: September 24, 2002Assignee: Oki Electric Industry Co., Ltd.Inventors: Azusa Yanagisawa, Koki Muto, Tadashi Nishimuro, Katsuo Oshima, Akira Watanabe, Akihiko Nara, Kouhei Shimoyama, Keisuke Tanaka, Takamitsu Furukawa, Shouzou Kobayashi