Abstract: The problem addressed by the present invention is to provide: an optical receptacle that can be easily positioned with a photoelectric converter having a light-emitting element and a detection element. In order to solve the problem, an optical receptacle is provided, said optical receptacle being positioned between a light transmission medium and a photoelectric converter having a substrate, a photoelectric conversion element and a detection element, and the purpose of the optical receptacle being to optically couple the photoelectric conversion element and the end surface of the light transmission medium. The optical receptacle comprises a filter, a holding member for holding the filter, and a receptacle body. In the optical receptacle the holding member and the receptacle body are separate bodies, and the filter reflects towards the detection element side, as monitor light, part of the light emitted from the photoelectric conversion element, and transmits the remainder as signal light.

Abstract: A work vehicle according to an embodiment includes: (i) a travelling vehicle body that includes a power source to a work part and a travel part; (ii) a communication unit that is able to transmit and receive signals to and from a portable communication terminal; and (iii) a control unit that is able to control the travel part on the basis of a signal transmitted from the portable communication terminal and received by the communication unit. A plurality of communication systems is provided between the communication unit and the portable communication terminal. The communication systems include a first communication system that is able to transmit a first signal from a portable communication terminal, and a second communication system that has a smaller communication area than that of the first communication system and is able to receive a second signal indicating that the portable communication terminal exists in a predetermined area.

Abstract: A speed change control apparatus for a work vehicle includes a hydraulic continuously variable speed transmission that performs speed change on power input from an engine by changing a trunnion shaft angle based on a depressing amount of a speed change pedal and outputs the power, a pedal position detector that detects a pedal position responsive to the depressing amount of the speed change pedal, and a control unit that controls a number of revolutions of the engine and the trunnion shaft angle of the hydraulic continuously variable speed transmission based on a detection value of the pedal position detector. The control unit performs control so that the trunnion shaft angle is maximized at a second pedal position set to a position shallower than a first pedal position at which the number of revolutions of the engine is maximized by a depressing operation of the speed change pedal.

Abstract: An information processing apparatus which includes a storage unit having stored a design data denoting layout and connection of a circuit, and a timing constraint data including a clock skew value denoting a delay difference allowed for a clock inputted to a pair of elements; a data read-out unit for reading out the design data and the timing constraint data; a clock skew value acquisition unit for acquiring the clock skew value set in correspondence with the pair of elements in layout in the circuit denoted by the design data from the timing constraint data; and a slack calculation unit for calculating a delay time between the pair of elements on the basis of the design data, and calculating a slack value indicating whether or not the pair of elements meets a predetermined design requirement by utilizing the acquired clock skew value and the calculated delay time with respect to the pair of elements.

Abstract: A timing analyzing system includes an RC extracting section configured to generate an SPEF (Standard Parasitic Exchange Format) file which contains resistance and capacitance components of wirings; a delay calculating section configured to generate an SDF (Standard Delay Format) file based on the SPEF file; and a clock mesh calculating section configured to generate a corrected circuit model by simplifying a netlist on a clock path to pass through a clock mesh structure from an input stage. A timing analysis section is configured to perform timing analysis of a semiconductor integrated circuit of an analysis target based on the corrected circuit model.

Abstract: An information processing apparatus which includes a storage unit having stored a design data denoting layout and connection of a circuit, and a timing constraint data including a clock skew value denoting a delay difference allowed for a clock inputted to a pair of elements; a data read-out unit for reading out the design data and the timing constraint data; a clock skew value acquisition unit for acquiring the clock skew value set in correspondence with the pair of elements in layout in the circuit denoted by the design data from the timing constraint data; and a slack calculation unit for calculating a delay time between the pair of elements on the basis of the design data, and calculating a slack value indicating whether or not the pair of elements meets a predetermined design requirement by utilizing the acquired clock skew value and the calculated delay time with respect to the pair of elements.

Abstract: An LSI (Large-Scale Integrated) circuit system capable of preventing antenna damage occurring in MOS (Metal Oxide Semiconductor) transistors due to an erroneous operation of a wiring formed during manufacturing processes of LSIs or like as an antenna. Layout data after installation of wirings is read by layout reading processing and up-sizing candidate table is created by sizing candidate table creating processing using various libraries so that candidate values are arranged for every function cell in ascending order of gate areas. By antenna error net detecting processing, a net having wiring layers causing an antenna error is detected. A gate pin, its instance, type of a cell connected to the net is recognized by gate pin/cell recognizing processing and a cell enabling prevention of an antenna error is up-sized by cell sizing processing by referring to a gate area stored in an up-sizing candidate table.

Abstract: A timing analyzing system includes an RC extracting section configured to generate an SPEF (Standard Parasitic Exchange Format) file which contains resistance and capacitance components of wirings; a delay calculating section configured to generate an SDF (Standard Delay Format) file based on the SPEF file; and a clock mesh calculating section configured to generate a corrected circuit model by simplifying a netlist on a clock path to pass through a clock mesh structure from an input stage. A timing analysis section is configured to perform timing analysis of a semiconductor integrated circuit of an analysis target based on the corrected circuit model.

Abstract: An LSI (Large-Scale Integrated) circuit system capable of preventing antenna damage occurring in MOS (Metal Oxide Semiconductor) transistors due to an erroneous operation of a wiring formed during manufacturing processes of LSIs or like as an antenna. Layout data after installation of wirings is read by layout reading processing and up-sizing candidate table is created by sizing candidate table creating processing using various libraries so that candidate values are arranged for every function cell in ascending order of gate areas. By antenna error net detecting processing, a net having wiring layers causing an antenna error is detected. A gate pin, its instance, type of a cell connected to the net is recognized by gate pin/cell recognizing processing and a cell enabling prevention of an antenna error is up-sized by cell sizing processing by referring to a gate area stored in an up-sizing candidate table.