Patents by Inventor Konrad Roesl
Konrad Roesl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088087Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Alexander HEINRICH, Michael JUERSS, Konrad ROESL, Oliver EICHINGER, Kok Chai GOH, Tobias SCHMIDT
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Patent number: 11842975Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.Type: GrantFiled: November 11, 2019Date of Patent: December 12, 2023Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Publication number: 20230130092Abstract: A semiconductor device includes: a semiconductor die having a metal region; a substrate having a metal region; and a soldered joint between the metal region of the semiconductor die and the metal region of the substrate. One or more intermetallic phases are present throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the semiconductor die and the metal region of the substrate. The soldered joint has the same length-to-width aspect ratio as the semiconductor die.Type: ApplicationFiled: December 20, 2022Publication date: April 27, 2023Inventors: Alexander Heinrich, Konrad Roesl, Kirill Trunov, Arthur Unrau
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Patent number: 11605608Abstract: A method of joining a semiconductor die to a substrate includes: applying a solder preform to a metal region of the semiconductor die or to a metal region of the substrate, the solder preform having a maximum thickness of 30 ?m and a lower melting point than both metal regions; forming a soldered joint between the metal region of the semiconductor die and the metal region of the substrate via a diffusion soldering process and without applying pressure directly to the die; and setting a soldering temperature of the diffusion soldering process so that the solder preform melts and fully reacts with the metal region of the semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the melting point of the preform and the soldering temperature.Type: GrantFiled: November 11, 2019Date of Patent: March 14, 2023Assignee: Infineon Technologies Austria AGInventors: Alexander Heinrich, Konrad Roesl, Kirill Trunov, Arthur Unrau
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Publication number: 20210375824Abstract: An electronic device includes: a first semiconductor die having a metal region; a substrate having a plurality of metal regions; a first soldered joint between the metal region of the first semiconductor die and a first metal region of the substrate, the first soldered joint having one or more intermetallic phases throughout the entire soldered joint, each of the one or more intermetallic phases formed from a solder preform diffused into the metal region of the first semiconductor die and the first metal region of the substrate; and a second semiconductor die soldered to the first or different metal region of the substrate.Type: ApplicationFiled: August 16, 2021Publication date: December 2, 2021Inventors: Kirill Trunov, Alexander Heinrich, Konrad Roesl, Arthur Unrau
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Patent number: 11158602Abstract: A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 ?m and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.Type: GrantFiled: November 11, 2019Date of Patent: October 26, 2021Assignee: Infineon Technologies Austria AGInventors: Kirill Trunov, Alexander Heinrich, Konrad Roesl, Arthur Unrau
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Publication number: 20210143123Abstract: A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 ?m and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.Type: ApplicationFiled: November 11, 2019Publication date: May 13, 2021Inventors: Kirill Trunov, Alexander Heinrich, Konrad Roesl, Arthur Unrau
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Publication number: 20210143120Abstract: A method of joining a semiconductor die to a substrate includes: applying a solder preform to a metal region of the semiconductor die or to a metal region of the substrate, the solder preform having a maximum thickness of 30 ?m and a lower melting point than both metal regions; forming a soldered joint between the metal region of the semiconductor die and the metal region of the substrate via a diffusion soldering process and without applying pressure directly to the die; and setting a soldering temperature of the diffusion soldering process so that the solder preform melts and fully reacts with the metal region of the semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the melting point of the preform and the soldering temperature.Type: ApplicationFiled: November 11, 2019Publication date: May 13, 2021Inventors: Alexander Heinrich, Konrad Roesl, Kirill Trunov, Arthur Unrau
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Publication number: 20200075530Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.Type: ApplicationFiled: November 11, 2019Publication date: March 5, 2020Inventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Patent number: 10475761Abstract: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.Type: GrantFiled: September 10, 2018Date of Patent: November 12, 2019Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Publication number: 20190006311Abstract: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.Type: ApplicationFiled: September 10, 2018Publication date: January 3, 2019Inventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Patent number: 9673170Abstract: Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier.Type: GrantFiled: August 5, 2014Date of Patent: June 6, 2017Assignee: Infineon Technologies AGInventors: Rupert Fischer, Peter Strobel, Joachim Mahler, Konrad Roesl, Alexander Heinrich
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Publication number: 20170025375Abstract: An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.Type: ApplicationFiled: September 30, 2016Publication date: January 26, 2017Inventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Patent number: 9490193Abstract: The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.Type: GrantFiled: December 1, 2011Date of Patent: November 8, 2016Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Michael Juerss, Konrad Roesl, Oliver Eichinger, Kok Chai Goh, Tobias Schmidt
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Publication number: 20160043054Abstract: Methods for connecting chips to a chip carrier are disclosed. In some embodiments the method for connecting a plurality of chips to a chip carrier includes placing first chips on a transfer carrier, placing second chips on the transfer carrier, placing the transfer carrier with the first and second chips on the chip carrier and forming connections between the first chips and the chip carrier and the second chips and the chip carrier.Type: ApplicationFiled: August 5, 2014Publication date: February 11, 2016Inventors: Rupert Fischer, Peter Strobel, Joachim Mahler, Konrad Roesl, Alexander Heinrich
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Self-aligning pick-up head and method for manufacturing a device with the self-aligning pick-up head
Patent number: 9079318Abstract: A self-aligning pick-up head, a method to manufacture a pick-up head and a method of manufacturing a device are disclosed. In one embodiment a pick-up head includes a nozzle having a first end portion and a second end portion and a base tool comprising a collet head, wherein the first end portion of the nozzle is gimbaled to the base tool.Type: GrantFiled: December 20, 2012Date of Patent: July 14, 2015Assignee: Infineon Technologies AGInventors: Horst Groeninger, Konrad Roesl -
Patent number: 9034751Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 ?m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.Type: GrantFiled: July 18, 2014Date of Patent: May 19, 2015Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Konrad Roesl, Oliver Eichinger
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Publication number: 20140329361Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 ?m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.Type: ApplicationFiled: July 18, 2014Publication date: November 6, 2014Inventors: Alexander Heinrich, Konrad Roesl, Oliver Eichinger
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Patent number: 8802553Abstract: A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 ?m. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.Type: GrantFiled: February 10, 2011Date of Patent: August 12, 2014Assignee: Infineon Technologies AGInventors: Alexander Heinrich, Konrad Roesl, Oliver Eichinger
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Self-Aligning Pick-up Head and Method for Manufacturing a Device with the Self-Aligning Pick-up Head
Publication number: 20140174652Abstract: A self-aligning pick-up head, a method to manufacture a pick-up head and a method of manufacturing a device are disclosed. In one embodiment a pick-up head includes a nozzle having a first end portion and a second end portion and a base tool comprising a collet head, wherein the first end portion of the nozzle is gimbaled to the base tool.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Horst Groeninger, Konrad Roesl