Patents by Inventor Konstantin Bourdelle
Konstantin Bourdelle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9698063Abstract: The invention concerns a method of testing a semiconductor-on-insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor-on-insulator type structures including carrying out the test on a sample structure from the batch.Type: GrantFiled: February 18, 2013Date of Patent: July 4, 2017Assignee: SOITECInventors: Patrick Reynaud, Walter Schwarzenbach, Konstantin Bourdelle, Jean-Francois Gilbert
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Patent number: 9275892Abstract: A method of transferring a layer from a donor substrate onto a receiving substrate comprises ionic implantation of at least one species into the donor substrate and forming a layer of concentration of the species intended to form microcavities or platelets; bonding the donor substrate with the receiving substrate by wafer bonding; and splitting at high temperature to split the layer in contact with the receiving substrate by cleavage, at a predetermined cleavage temperature, at the layer of microcavities or platelets formed in the donor substrate. The method further comprises, after the first implantation step and before the splitting step, ionic implantation of silicon ions into the donor substrate to form a layer of concentration of silicon ions in the donor substrate, the layer of concentration of silicon ions at least partially overlapping the layer of concentration of the species intended to form microcavities or platelets.Type: GrantFiled: November 23, 2011Date of Patent: March 1, 2016Assignee: SOITECInventors: Nicolas Daix, Konstantin Bourdelle
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Patent number: 9035474Abstract: The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor substrate and the handle substrate to obtain a donor-handle compound.Type: GrantFiled: June 3, 2010Date of Patent: May 19, 2015Assignee: SoitecInventors: Carlos Mazure, Richard Ferrant, Konstantin Bourdelle, Bich-Yen Nguyen
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Patent number: 9018678Abstract: The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.Type: GrantFiled: February 17, 2012Date of Patent: April 28, 2015Assignee: SoitecInventors: Nicolas Daval, Bich-Yen Nguyen, Cecile Aulnette, Konstantin Bourdelle
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Publication number: 20150014822Abstract: The invention concerns a method of testing a semiconductor on insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor on insulator type structures including carrying out the test on a sample structure from the batch.Type: ApplicationFiled: February 18, 2013Publication date: January 15, 2015Applicant: SOITECInventors: Patrick Reynaud, Walter Schwarzenbach, Konstantin Bourdelle, Jean-Francois Gilbert
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Publication number: 20140284768Abstract: A semiconductor structure comprising a first semiconductor layer, a bulk semiconductor layer, an insulation layer between the first semiconductor layer and the bulk semiconductor layer, a first implanted region that is at least partially within the insulation layer; and a second doped region that is at least partially within the bulk semiconductor layer, wherein the first implanted region has an implant profile that shows a maximum within the insulation layer and a tail extending within the bulk semiconductor layer so as to inhibit the diffusion of a second doping material of the second doped region within the insulation layer.Type: ApplicationFiled: November 13, 2012Publication date: September 25, 2014Applicant: SOITECInventor: Konstantin Bourdelle
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Publication number: 20130302970Abstract: A method of transferring a layer from a donor substrate onto a receiving substrate comprises ionic implantation of at least one species into the donor substrate and forming a layer of concentration of the species intended to form microcavities or platelets; bonding the donor substrate with the receiving substrate by wafer bonding; and splitting at high temperature to split the layer in contact with the receiving substrate by cleavage, at a predetermined cleavage temperature, at the layer of microcavities or platelets formed in the donor substrate. The method further comprises, after the first implantation step and before the splitting step, ionic implantation of silicon ions into the donor substrate to form a layer of concentration of silicon ions in the donor substrate, the layer of concentration of silicon ions at least partially overlapping the layer of concentration of the species intended to form microcavities or platelets.Type: ApplicationFiled: November 23, 2011Publication date: November 14, 2013Applicant: SOITECInventors: Nicolas Daix, Konstantin Bourdelle
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Patent number: 8309426Abstract: The present invention provides methods for the manufacture of a trench structure in a multilayer wafer that comprises a substrate, an oxide layer on the substrate and a semiconductor layer on the oxide layer. These methods include the steps of forming a trench through the semiconductor layer and the oxide layer and extending into the substrate, and of performing an anneal treatment of the formed trench such that at the inner surface of the trench some material of the semiconductor layer flows at least over a portion of the part of the oxide layer exposed at the inner surface of the trench. Substrates manufactured according to this invention are advantageous for fabricating various semiconductor devices, e.g., MOSFETs, trench capacitors, and the like.Type: GrantFiled: April 25, 2011Date of Patent: November 13, 2012Assignee: SoitecInventors: Konstantin Bourdelle, Carlos Mazure
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Patent number: 8309431Abstract: A method for self-supported transfer of a fine layer, in which at least one species of ions is implanted in a source-substrate at a specified depth in relation to the surface of the source-substrate. A stiffener is applied in intimate contact with the source-substrate and the source-substrate undergoes a heat treatment at a specified temperature during a specified period of time in order to create an embrittled buried area substantially at the specified depth without causing a thin layer, defined between the surface and the embrittled buried layer in relation to the remainder of the source-substrate, to become thermally detached. A controlled localized energy pulse is applied to the source-substrate in order to cause the self-supported detachment of the thin layer.Type: GrantFiled: October 28, 2004Date of Patent: November 13, 2012Assignee: Commissariat a l'Energie AtomiqueInventors: Nguyet-Phuong Nguyen, Ian Cayrefourcq, Christelle Lagahe-Blanchard, Konstantin Bourdelle, Aurélie Tauzin, Franck Fournel
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Publication number: 20120228672Abstract: The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, a N Field-Effect Transistor (NFET), a method for manufacturing a NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.Type: ApplicationFiled: February 17, 2012Publication date: September 13, 2012Applicant: SOITECInventors: Nicolas Daval, Bich-Yen Nguyen, Cecile Aulnette, Konstantin Bourdelle
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Patent number: 8263475Abstract: A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating the substrate(s) that contains the silicon oxide layer at 900° C. to 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen to form layer trapping through-holes inside the silicon oxide, bonding the substrates together at a bonding interface with the silicon oxide layer(s) positioned between them, reinforcing the bonding by annealing the substrates at 25° C. to 500° C. such that the trapping holes retaining gas species at the bonding interface, and transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure.Type: GrantFiled: January 27, 2009Date of Patent: September 11, 2012Assignee: SoitecInventors: Ionut Radu, Oleg Kononchuk, Konstantin Bourdelle
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Patent number: 8241942Abstract: A method of fabricating a back-illuminated image sensor that includes the steps of providing a first substrate of a semiconductor layer, in particular a silicon layer, forming electronic device structures over the semiconductor layer and, only then, doping the semiconductor layer. By doing so, improved dopant profiles and electrical properties of photodiodes can be achieved such that the final product, namely an image sensor, has a better quality.Type: GrantFiled: September 22, 2009Date of Patent: August 14, 2012Assignee: SoitecInventors: Konstantin Bourdelle, Carlos Mazure
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Publication number: 20110294277Abstract: The present invention provides methods for the manufacture of a trench structure in a multilayer wafer that comprises a substrate, an oxide layer on the substrate and a semiconductor layer on the oxide layer. These methods include the steps of forming a trench through the semiconductor layer and the oxide layer and extending into the substrate, and of performing an anneal treatment of the formed trench such that at the inner surface of the trench some material of the semiconductor layer flows at least over a portion of the part of the oxide layer exposed at the inner surface of the trench. Substrates manufactured according to this invention are advantageous for fabricating various semiconductor devices, e.g., MOSFETs, trench capacitors, and the like.Type: ApplicationFiled: April 25, 2011Publication date: December 1, 2011Inventors: Konstantin Bourdelle, Carlos Mazure
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Publication number: 20110287571Abstract: A method of fabricating a back-illuminated image sensor that includes the steps of providing a first substrate of a semiconductor layer, in particular a silicon layer, forming electronic device structures over the semiconductor layer and, only then, doping the semiconductor layer. By doing so, improved dopant profiles and electrical properties of photodiodes can be achieved such that the final product, namely an image sensor, has a better quality.Type: ApplicationFiled: September 22, 2009Publication date: November 24, 2011Applicant: S.O.I.TEC Silicon On Insulator TechnologiesInventors: Konstantin Bourdelle, Carlos Mazure
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Patent number: 8058158Abstract: A method for manufacturing a hybrid semiconductor substrate comprises the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby, a higher number of process steps involved in the manufacturing process of hybrid semiconductor substrates may be avoided.Type: GrantFiled: March 18, 2010Date of Patent: November 15, 2011Assignee: S.O.I.TEC Silicon on Insulator TechnologiesInventors: Konstantin Bourdelle, Bich-Yen Nguyen, Mariam Sadaka
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Publication number: 20110241157Abstract: The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound.Type: ApplicationFiled: June 3, 2010Publication date: October 6, 2011Inventors: Carlos Mazure, Richard Ferrant, Konstantin Bourdelle, Bich-Yen Nguyen
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Publication number: 20110165758Abstract: The invention relates to a method for making a structure for use ion applications in the fields of electronics, optics or optoelectronics. The structure includes a thin layer of semiconducting material on a supporting substrate. The method includes bonding the thin layer onto the supporting substrate by molecular adhesion at a bonding interface to obtain a structure; implanting ions at the bonding interface to transfer atoms from the thin layer to transfer atoms between the thin layer and the supporting substrate or vice versa; and heat-treating the structure in order to stabilize the bonding interface.Type: ApplicationFiled: July 3, 2009Publication date: July 7, 2011Inventors: Konstantin Bourdelle, Didier Landru, Karine Landry
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Patent number: 7871900Abstract: A method for forming a structure is provided and includes implanting an atomic species into a donor substrate having an upper surface at a given depth relative to the upper surface to form an embrittlement zone in the donor substrate, the embrittlement zone defining a removable layer within the donor substrate. The method further includes assembling the upper surface of the donor substrate to a receiver substrate. Additionally, the method includes detaching the removable layer from the donor substrate at the embrittlement zone, thereby forming a detachment surface on the removable layer, by high temperature annealing. The high temperature annealing includes a temperature upgrade phase to a predetermined maximum temperature, maintaining the maximum temperature for a predetermined exposure duration, and a temperature downgrade phase. The maximum temperature and the exposure duration are selected so as to prevent the appearance of significant defects at the detachment surface.Type: GrantFiled: October 16, 2007Date of Patent: January 18, 2011Assignee: S.O.I. Tec Silicon on Insulator TechnologiesInventors: Konstantin Bourdelle, Nguyet-Phuong Nguyen, Walter Schwarzenbach
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Publication number: 20100289113Abstract: The present invention relates to a method for manufacturing a hybrid semiconductor substrate comprising the steps of (a) providing a hybrid semiconductor substrate comprising a semiconductor-on-insulator (SeOI) region, that comprises an insulating layer over a base substrate and a SeOI layer over the insulating layer, and a bulk semiconductor region, wherein the SeOI region and the bulk semiconductor region share the same base substrate; (b) providing a mask layer over the SeOI region; and (c) forming a first impurity level by doping the SeOI region and the bulk semiconductor region simultaneously such that the first impurity level in the SeOI region is contained within the mask. Thereby avoiding higher number of process steps involved in the manufacturing process of hybrid semiconductor substrate.Type: ApplicationFiled: March 18, 2010Publication date: November 18, 2010Applicant: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Konstantin Bourdelle, Bich-Yen Nguyen, Mariam Sadaka
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Patent number: 7833877Abstract: This invention relates to a method for producing a substrate by transferring a layer of a material from a donor substrate to a support substrate, and then by removing a part of the layer of material to form the thin layer. The step of removing a part of the layer of material to form the thin layer comprises forming an amorphous layer in a part of the thin layer, and then recrystallizing the amorphous layer.Type: GrantFiled: October 23, 2007Date of Patent: November 16, 2010Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Konstantin Bourdelle, Carlos Mazure