Abstract: An analog-to-digital converter comprises a signal input (6) for receiving an analog input signal and a set of comparators (4). Each comparator (4) has a first input (21) connected to the signal input (6) and a second input (22) connected to a reference voltage (16). Each comparator generates an output based on the comparison of the signals at the first input (21) and second input (22). The reference voltage is the same for all comparators. The set of comparators (4) has a non-identical response to the reference voltage (16) and the input signal and is due to an internally arising offset. An adder (25) determines a sum of the outputs of the set of comparators and conversion logic (27) generates an output digital signal dependent on the determined sum. Multiple sets of comparators can be provided, each set having a different respective reference voltage.

Abstract: A device for receiving a RF signal (1; 21) with loop-through output (16) is provided. The device comprises: an input (3) receiving a RF input signal (2); an analog-digital converter (8) converting the RF input signal (2) to a digital signal (9); a digital signal processing unit (10) digitally processing the digital signal (9); a digital-analog converter (14) converting the processed digital signal (13) to a loop-through RF signal (15) corresponding to the RF input signal (2); and a loop-through output (16) outputting the loop-through RF signal (15).

Abstract: A multi-channel receiver comprising an ADC and a multi-band, multi-channel selector. The ADC converts a broad-band multi-channel signal into a digital signal. The digital signal is then broken into sub-bands each containing a plurality of channels. A channel selector selects desired channels from the appropriate sub-band. The multi-channel receiver may deliver simultaneous channels equal to the number of channel selectors that have been implemented. The multi-channel receiver may be implemented on a single integrated circuit.

Abstract: This invention relates to Analog to Digital Converters (ADC) and, inter alia, to Time Interleaved ADCs and Successive Approximation Register (SAR) ADC's. In a conventional Time Interleaved ADC employing SAR ADC units, the input signal is processed through a track-and-hold circuit (T/H), and then through a buffer circuit, before the SAR ADC unit. There, by means of a comparator, the signal is compared with a Digital-to-Analog Converter (DAC) signal from the SAR logic. The buffer reduces the influence of capacitive loading and physical layout design on the SAR ADC input, but typically has a non-linear response and thus introduces distortion to the input signal. This can limit the ADC linearity, particularly for high-speed ADCs operating with low-supply voltages. An objective of the invention is to reduce or eliminate the effect of the buffer non-linearity. This is done in some embodiments by routing both the signals to the comparator through the same buffer circuit.

Abstract: A device (100) for processing data, the device (100) comprising a plurality of signal paths (130, 140, 150) each receiving an identical analog input signal (104), at least one signal conditioning unit (101 to 103) in at least one of the plurality of signal paths (130, 140, 150), wherein each signal conditioning unit (101 to 103) is adapted for generating a respective analog intermediate signal (105 to 107) by manipulating a property, particularly an amplitude, of the analog input signal (104), and a plurality of analog to digital converting units (108 to 110) each of which being assigned to a corresponding one of the plurality of signal paths (130, 140, 150) and being supplied with the analog input signal (104) or a respective analog intermediate signal (105 to 107), wherein each of the plurality of analog to digital converting units (108 to 110) is adapted for generating a respective digital intermediate signal (111 to 113) based on the respective analog intermediate signal (105 to 107) or based on the analo

Abstract: A method of performing a service scan for available channels across a bandwidth of an input signal, the method comprising the steps of: acquiring a power spectrum of the input signal bandwidth; analysing the power spectrum to identify a list of candidate channels, each candidate channel being identified by at least a centre frequency; processing each of the candidate channels in a receiver unit to extract service information, if present, relating to the candidate channel; and storing the service information for the channel in a memory.

Abstract: An analog-to-digital converter comprises a signal input (6) for receiving an analog input signal and a set of comparators (4). Each comparator (4) has a first input (21) connected to the signal input (6) and a second input (22) connected to a reference voltage (16). Each comparator generates an output based on the comparison of the signals at the first input (21) and second input (22). The reference voltage is the same for all comparators. The set of comparators (4) has a non-identical response to the reference voltage (16) and the input signal and is due to an internally arising offset. An adder (25) determines a sum of the outputs of the set of comparators and conversion logic (27) generates an output digital signal dependent on the determined sum. Multiple sets of comparators can be provided, each set having a different respective reference voltage.

Abstract: A device for receiving a RF signal (1; 21) with loop-through output (16) is provided. The device comprises: an input (3) receiving a RF input signal (2); an analog-digital converter (8) converting the RF input signal (2) to a digital signal (9); a digital signal processing unit (10) digitally processing the digital signal (9); a digital-analog converter (14) converting the processed digital signal (13) to a loop-through RF signal (15) corresponding to the RF input signal (2); and a loop-through output (16) outputting the loop-through RF signal (15).

Abstract: The present invention relates to a signal processing apparatus comprising a signal input and a signal output; a plurality of signal processing units, wherein each signal processing unit having the same structure and at least one spatial error, being connected to the signal input, and being adapted to subject an input signal from the signal input to predetermined signal processing; selection means configured to select and form a predetermined number of groups from the plurality of signal processing units in accordance with a predetermined criterion; and control means for controlling the groups of the signal processing units to be active in a time interleaved schema, wherein an active group provides a respective processed input signal as an output signal to the signal output; wherein the plurality of signal processing units comprises more signal processing units as required to realize a predetermined time interleaving factor.

Abstract: A device (100) for processing data, the device (100) comprising a plurality of signal paths (130, 140, 150) each receiving an identical analog input signal (104), at least one signal conditioning unit (101 to 103) in at least one of the plurality of signal paths (130, 140, 150), wherein each signal conditioning unit (101 to 103) is adapted for generating a respective analog intermediate signal (105 to 107) by manipulating a property, particularly an amplitude, of the analog input signal (104), and a plurality of analog to digital converting units (108 to 110) each of which being assigned to a corresponding one of the plurality of signal paths (130, 140, 150) and being supplied with the analog input signal (104) or a respective analog intermediate signal (105 to 107), wherein each of the plurality of analog to digital converting units (108 to 110) is adapted for generating a respective digital intermediate signal (111 to 113) based on the respective analog intermediate signal (105 to 107) or based on the analo