Abstract: A transistor comprises a layered semiconductor structure electrically connected to a plurality of electrodes forming a source, a gate, and a drain of the transistor. The layered semiconductor structure includes a channel layer having a shape formed by a set of fins, and a barrier layer on the channel layer such that the barrier layer coats the fins of the channel layer to define a shape formed by a series of wells. The series of wells of the barrier layer are interdigitated with the series of fins of the channel layer. The barrier layer is formed with polar piezoelectric material having a first lattice constant and the channel layer is formed with polar material having a second lattice constant, where the second lattice constant is greater than the first lattice constant.

Abstract: A compound transistor comprises a plurality of electrodes, a first semiconductor structure, and a second semiconductor structure. The electrodes include a source, a gate, and a drain of a first transistor. The first semiconductor structure is electrically connected to the plurality of electrodes and includes a barrier layer and a first channel layer. The second semiconductor structure includes a second channel layer, a buffer layer, and a substrate layer arranged such that the buffer layer is sandwiched between the second channel layer and the substrate layer. The second transistor structure supports the first semiconductor structure such that a connecting layer is arranged between the first and the second semiconductor structures. A source electrode is electrically connected to the second channel layer such that the source of the first transistor forms a base of a second transistor, and the source electrode forms a collector of the second transistor.

Abstract: The present disclosure discloses a negative inductor device. The negative inductor device comprises a negative inductor comprising a ferromagnetic material and a conductive material arranged inside the ferromagnetic material. The negative inductor device further comprises a current limiting circuit electrically coupled to the negative inductor and configured to supply an electric current of magnitude within a range, the range being defined by a first local minimum and a second local minimum of a current-energy curve of the ferromagnetic material.

Abstract: The present disclosure discloses a semiconductor device comprising a plurality of epitaxial layers including a barrier layer and a channel layer such that two-dimensional carrier densities are formed at an interface of the barrier layer and the channel layer, wherein a priority of charge carriers of the channel layer is based on a polarization direction of the barrier layer, and wherein the polarization direction of the barrier layer can be changed by applying an electric field across the barrier layer. The semiconductor device further comprises a first source terminal and a second source terminal, wherein in one of the first source terminal and the second source terminal is ohmic to electrons and other one is ohmic to holes. The semiconductor device further comprises a first drain terminal and a second drain terminal, a gate terminal, and a set terminal ohmic to the channel layer.

Abstract: Devices and methods of a transistor device including a source and a drain, the source and drain are at a horizontal plane at a location along a vertical direction. A gate, that is at a higher horizontal plane along the vertical direction then the source and drain horizontal plane. A first region under the source and drain horizontal plane, includes a first three Nitride (III-N) layer, a second III-N layer over the first III-N layer. A second region under the gate, includes a first III-N layer, a second III-N layer over the first III-N layer, and a third III-N layer over the second III-N layer. The third III-N layer at selective locations extends through the second III-N layer and into a portion of the first III-N layer along a width of the transistor. The third III-N layer is doped P-type, and the first and second III-N layers are unintentionally doped.

Abstract: The present disclosure discloses a negative inductor device. The negative inductor device comprises a negative inductor comprising a ferromagnetic material and a conductive material arranged inside the ferromagnetic material. The negative inductor device further comprises a current limiting circuit electrically coupled to the negative inductor and configured to supply an electric current of magnitude within a range, the range being defined by a first local minimum and a second local minimum of a current-energy curve of the ferromagnetic material.

Abstract: Semiconductor devices includes third arms. A channel from the first and second arms extends to a channel of the third arm. When a current from a first voltage is flowing from the first arm to the second arm, a flow of ballistic electrons is generated that flow through the third arm channel from the channel of the first and second arms to the third arm channel. A fin structure located in the third arm channel and includes a gate. The gate is controlled using a second voltage over the fin structure, the fin structure is formed to induce an energy-field structure that shifts by an amount of the second voltage to control an opening of the gate that the flow of ballistic electrons pass through, which in turn changes a depletion width, subjecting the ballistic electrons to diffraction, and then interference.

Abstract: A motor comprising a shaft, an array of stator assemblies rigidly attached to the shaft, each stator assembly includes a stator yoke having a toroid shape fixed around the shaft and having a number of slots at radial and axis directional faces with windings within the slots of the stator yoke, and a rotor assembly rotatively attached to the shaft to enclose the array of stator assemblies, the rotor assembly has a rotor drum with sections, each section embraces one stator assembly, each section has two axial-flux permanent magnet arrays attached on axial-directional inner surfaces of the section and has one radial-flux permanent magnet array attached on a radial-directional inner surface of the section furthest from the shaft, wherein the axial-flux and the radial-flux permanent magnet arrays with the number of pole pairs equals the number of the stator slots plus or minus the number of stator winding pole pair.

Abstract: An AND-gate device having a structure arms, a channel from a first arm and a second arm extends to a channel of a third arm. When a current from a first voltage flowing from a first electrode of the first arm to a second electrode of the second arm, a flow of electrons is generated that flows through the third arm channel from the channel of the first and second arms to the third arm channel. At least two input structures are positioned in series in the third arm. Each input structure includes a fin structure having a gate controlled by an individual voltage applied to an electrode which induces an electric-field structure that shifts by an amount of the voltage. The controllable gate opening changes a depletion width, causing an amount of flow of ballistic electrons to pass through the channel. A sensor detects the ballistic electrons.

Abstract: Semiconductor devices including a first region having a first three Nitride (III-N) layer and a second III-N layer, the second III-N layer is over the first III-N. The second III-N layer has spontaneous polarization less than the first III-N layer, such that a two-dimensional hole gas (2-DHG) will be formed at a junction of the first III-N layer to the second III-N layer. An Anode forms an ohmic contact to the 2-DHG. A second region includes a third III-N layer and a forth III-N layer, such that the fourth III-N layer is over the third III-N. The forth III-N layer has spontaneous polarization greater than the third III-N layer, such that two-dimensional electron gas (2-DEG) will be formed at a junction of the third III-N layer to the forth III-N layer. A Cathode forms an ohmic contact to the 2-DEG. The first and second regions are connected at an interface.

Abstract: A motor comprising a shaft, an array of stator assemblies rigidly attached to the shaft, each stator assembly includes a stator yoke having a toroid shape fixed around the shaft and having a number of slots at radial and axis directional faces with windings within the slots of the stator yoke, and a rotor assembly rotatively attached to the shaft to enclose the array of stator assemblies, the rotor assembly has a rotor drum with sections, each section embraces one stator assembly, each section has two axial-flux permanent magnet arrays attached on axial-directional inner surfaces of the section and has one radial-flux permanent magnet array attached on a radial-directional inner surface of the section furthest from the shaft, wherein the axial-flux and the radial-flux permanent magnet arrays with the number of pole pairs equals the number of the stator slots plus or minus the number of stator winding pole pair.

Abstract: Semiconductor devices including a first region having a first three Nitride (III-N) layer and a second III-N layer, the second III-N layer is over the first III-N. The second III-N layer has spontaneous polarization less than the first III-N layer, such that a two-dimensional hole gas (2-DHG) will be formed at a junction of the first III-N layer to the second III-N layer. An Anode forms an ohmic contact to the 2-DHG. A second region includes a third III-N layer and a forth III-N layer, such that the fourth III-N layer is over the third III-N. The forth III-N layer has spontaneous polarization greater than the third III-N layer, such that two-dimensional electron gas (2-DEG) will be formed at a junction of the third III-N layer to the forth III-N layer. A Cathode forms an ohmic contact to the 2-DEG. The first and second regions are connected at an interface.

Abstract: Devices and methods of a transistor device including a source and a drain, the source and drain are at a horizontal plane at a location along a vertical direction. A gate, that is at a higher horizontal plane along the vertical direction then the source and drain horizontal plane. A first region under the source and drain horizontal plane, includes a first three Nitride (III-N) layer, a second III-N layer over the first III-N layer. A second region under the gate, includes a first III-N layer, a second III-N layer over the first III-N layer, and a third III-N layer over the second III-N layer. The third III-N layer at selective locations extends through the second III-N layer and into a portion of the first III-N layer along a width of the transistor. The third III-N layer is doped P-type, and the first and second III-N layers are unintentionally doped.

Abstract: Semiconductor devices includes third arms. A channel from the first and second arms extends to a channel of the third arm. When a current from a first voltage is flowing from the first arm to the second arm, a flow of ballistic electrons is generated that flow through the third arm channel from the channel of the first and second arms to the third arm channel. A fin structure located in the third arm channel and includes a gate. The gate is controlled using a second voltage over the fin structure, the fin structure is formed to induce an energy-field structure that shifts by an amount of the second voltage to control an opening of the gate that the flow of ballistic electrons pass through, which in turn changes a depletion width, subjecting the ballistic electrons to diffraction, and then interference.

Abstract: An AND-gate device having a structure arms, a channel from a first arm and a second arm extends to a channel of a third arm. When a current from a first voltage flowing from a first electrode of the first arm to a second electrode of the second arm, a flow of electrons is generated that flows through the third arm channel from the channel of the first and second arms to the third arm channel. At least two input structures are positioned in series in the third arm. Each input structure includes a fin structure having a gate controlled by an individual voltage applied to an electrode which induces an electric-field structure that shifts by an amount of the voltage. The controllable gate opening changes a depletion width, causing an amount of flow of ballistic electrons to pass through the channel. A sensor detects the ballistic electrons.

Abstract: A system for estimating a severity of a bearing fault in an induction motor, uses a set of filters and a set of quantitative models designed for a set of fault frequencies. The system, upon receiving the measurements of the stator current, extracts the first fault current from the stator current using the first filter, determine the first mutual inductance variation from the first fault current using the first quantitative model, and classify the first mutual inductance variation with the fault severity classifier to determine the severity of a first type of fault in the induction motor. Similarly, the system classifies a second type of fault using the second filter and the second quantitative model. The system outputs one or combination of the severity of the first type of fault in the induction motor and the severity of the second type of fault in the induction motor.

Abstract: An OR-gate device includes two cross shaped structures, each cross shaped structure includes a channel. Where at an end of each channel is an ohmic contact connecting the two cross shaped structures. Each cross shaped structure includes an epitaxial layer including a III-N heterostructure such as InAlN/GaN. Wherein an amount of an In concentration of the InAlN/GaN is tuned to lattice match with GaN, resulting in electron mobility to generate ballistic electrons. A fin structure located in the channel includes a gate formed transversely to a longitudinal axis of the channel. The gate is controlled using a voltage over the fin structure. Wherein the fin structure is formed to induce an energy-field structure that shifts by an amount of the voltage to control an opening of the gate that the flow of ballistic electrons is passing through, which in turn changes a depletion width, subjecting the ballistic electrons to interference.

Abstract: A transistor includes a gate electrode with multiple metals distributed along the width of the gate electrode. Each of the metals in the gate electrode has different work functions. Such a compound gate provides higher linearity when, e.g., operated as a radio frequency transistor.

Abstract: Devices, system and methods a circuit, including a resistor, a normal capacitor and a ferroelectric capacitor connected in series. An input terminal to provide an input voltage across the circuit. An output terminal to deliver an output voltage taken across the normal capacitor. The circuit comprises a ferroelectric layer sandwiched between a first buffer layer and a second buffer layer. The first buffer layer contacts a portion of a first metal layer and first metal layer extends beyond the first buffer layer. A dielectric layer sandwiched between a second metal layer and a third metal layer. Such that the second metal layer extends beyond the dielectric layer and in contact with the second buffer layer. Wherein the ferroelectric capacitor is formed by the first metal layer. The ferroelectric layer sandwiched between the first buffer layer and the second buffer layer, and the second metal layer.

Abstract: A high electron mobility transistor includes a set of electrodes, such as a source, a drain, a top gate, and a side gate, and includes a semiconductor structure having a fin extending between the source and the drain. The top gate is arranged on top of the fin, and the side gate is arranged on a sidewall of the fin at a distance from the top gate. The semiconductor structure includes a cap layer positioned beneath the top gate and a channel layer arranged beneath the cap layer for providing electrical conduction. The cap layer includes nitride-based semiconductor material to enable a heterojunction forming a carrier channel between the source and the drain.