Patents by Inventor Koshi Tamamura

Koshi Tamamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090250790
    Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs. Ordinary one-surface polishing having the steps of gluing a wafer with a surface on a flat disc, bringing another surface in contact with a lower turntable, pressing the disc, rotating the disc, revolving the turntable and whetting the lower surface, cannot remedy the inherent distortion. The Distortion worsens morphology of epitaxial wafers, lowers yield of via-mask exposure and invites cracks on surfaces. Nitride crystals are rigid but fragile. Chemical/mechanical polishing has been requested in vain.
    Type: Application
    Filed: February 27, 2009
    Publication date: October 8, 2009
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SONY CORPORATION
    Inventors: Masahiro NAKAYAMA, Naoki Matsumoto, Koshi Tamamura, Masao Ikeda
  • Patent number: 7535082
    Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs. Ordinary one-surface polishing having the steps of gluing a wafer with a surface on a flat disc, bringing another surface in contact with a lower turntable, pressing the disc, rotating the disc, revolving the turntable and whetting the lower surface, cannot remedy the inherent distortion. The Distortion worsens morphology of epitaxial wafers, lowers yield of via-mask exposure and invites cracks on surfaces. Nitride crystals are rigid but fragile. Chemical/mechanical polishing has been requested in vain.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: May 19, 2009
    Assignees: Sumitomo Electric Industries, Ltd., Sony Corporation
    Inventors: Masahiro Nakayama, Naoki Matsumoto, Koshi Tamamura, Masao Ikeda
  • Publication number: 20090059985
    Abstract: An n-type cladding layer structure which has good luminescence properties without the use of substances corresponding to RoHS Directive and a high Cl-doping efficiency, i.e. which facilitates the manufacture of a semiconductor optical element and device with low crystal defects and high reliability, and an active layer and a p-type cladding layer therefor are provided. The n-type layer being lattice matched to an InP substrate and containing Group II-VI compound as a main ingredient is a Group II-VI compound semiconductor, in which the Group II elements consist of Mg, Zn, and Be and the Group VI elements consist of Se and Te. The n-type layer of the present invention is characterized by a large energy gap, high energy of the bottom of a conduction band that is effective for suppress the Type II luminescence, high carrier concentration, and low crystal defects attributed to a good quality crystallinity.
    Type: Application
    Filed: February 27, 2008
    Publication date: March 5, 2009
    Inventors: Katsumi Kishino, Ichiro Nomura, Tsunenori Asatsuma, Kunihiko Tasai, Koshi Tamamura, Hiroshi Nakajima, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa
  • Publication number: 20080298415
    Abstract: A semiconductor device having high reliability, a long lifetime and superior light emitting characteristics by applying a novel material to a p-type cladding layer is provided. A semiconductor device includes a p-type semiconductor layer on an InP substrate, in which the p-type semiconductor layer has a laminate structure formed by alternately laminating a first semiconductor layer mainly including Bex1Mgx2Znx3Te (0<x1<1, 0<x2<1, 0<x3<1, x1+x2+x3=1) and a second semiconductor layer mainly including Bex4Mgx5Znx6Te (0<x4<1, 0<x5<1, 0<x6<1, x4+x5+x6=1).
    Type: Application
    Filed: June 3, 2008
    Publication date: December 4, 2008
    Applicants: SONY CORPORATION, HITACHI, LTD, SOPHIA SCHOOL CORPORATION
    Inventors: Katsumi Kishino, Ichiro Nomura, Koshi Tamamura, Kunihiko Tasai, Tsunenori Asatsuma, Hitoshi Nakamura, Sumiko Fujisaki, Takeshi Kikawa
  • Publication number: 20080247434
    Abstract: A semiconductor light-emitting device capable of increasing the carrier concentration of a p-type cladding layer and improving light-emitting efficiency is provided. A semiconductor light-emitting device is made of a Group II-VI compound semiconductor, and the semiconductor light-emitting device includes an active layer between an n-type cladding layer and a p-type cladding layer, in which the active layer has a Type II superlattice structure, and the junctions between the active layer and the n-type cladding layer and between the active layer and the p-type cladding layer each have a Type I structure, and the p-type cladding layer includes tellurium (Te) as a Group VI element.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 9, 2008
    Applicants: SONY CORPORATION, HITACHI, LTD, SOPHIA SCHOOL CORPORATION
    Inventors: Katsumi Kishino, Ichiro Nomura, Kunihiko Tasai, Koshi Tamamura, Hiroshi Nakajima, Hitoshi Nakamura
  • Publication number: 20070117357
    Abstract: When a semiconductor light emitting device or a semiconductor device is manufactured by growing nitride III-V compound semiconductor layers, which will form a light emitting device structure or a device structure, on a nitride III-V compound semiconductor substrate composed of a first region in form of a crystal having a first average dislocation density and a plurality of second regions having a second average dislocation density higher than the first average dislocation density and periodically aligned in the first region, device regions are defined on the nitride III-V compound semiconductor substrate such that the device regions do not substantially include second regions, emission regions or active regions of devices finally obtained do not include second regions.
    Type: Application
    Filed: January 23, 2007
    Publication date: May 24, 2007
    Inventors: Tsunenori Asatsuma, Shigetaka Tomiya, Koshi Tamamura, Tsuyoshi Tojo, Osamu Goto, Kensaku Motoki
  • Publication number: 20070051937
    Abstract: The present invention aims at providing a structure in which a high p-type carrier concentration of 1×1017 cm?3 or more is obtained in a material in which, although it shows normally p-type conductivity, a carrier concentration smaller than 1×1017 cm?3 is only obtained. Also, the present invention aims at providing highly reliable semiconductor element and device each of which has excellent characteristics such as light emitting characteristics and a long lifetime. Each specific layer, i.e., each ZnSe0.53Te0.47 layer (2ML) is inserted between host layers, i.e., Mg0.5Zn0.29Cd0.21Se layers (each having 10ML (atomic layer) thickness) each of which is lattice matched to an InP substrate. In this case, each specific layer in which a sufficient carrier concentration of 1×1018 cm?3 or more is obtained when a single layer is inserted at suitable intervals.
    Type: Application
    Filed: August 8, 2006
    Publication date: March 8, 2007
    Inventors: Katsumi Kishino, Ichiro Nomura, Koshi Tamamura, Hitoshi Nakamura
  • Patent number: 7176499
    Abstract: When a semiconductor light emitting device or a semiconductor device is manufactured by growing nitride III-V compound semiconductor layers, which will form a light emitting device structure or a device structure, on a nitride III-V compound semiconductor substrate composed of a first region in form of a crystal having a first average dislocation density and a plurality of second regions having a second average dislocation density higher than the first average dislocation density and periodically aligned in the first region, device regions are defined on the nitride III-V compound semiconductor substrate such that the device regions do not substantially include second regions, emission regions or active regions of devices finally obtained do not include second regions.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: February 13, 2007
    Assignees: Sony Corporation, Sumitomo Electric Industries, Ltd.
    Inventors: Tsunenori Asatsuma, Shigetaka Tomiya, Koshi Tamamura, Tsuyoshi Tojo, Osamu Goto, Kensaku Motoki
  • Patent number: 7091056
    Abstract: When a semiconductor light emitting device or a semiconductor device is manufactured by growing nitride III–V compound semiconductor layers, which will form a light emitting device structure or a device structure, on a nitride III–V compound semiconductor substrate composed of a first region in form of a crystal having a first average dislocation density and a plurality of second regions having a second average dislocation density higher than the first average dislocation density and periodically aligned in the first region, device regions are defined on the nitride III–V compound semiconductor substrate such that the device regions do not substantially include second regions, emission regions or active regions of devices finally obtained do not include second regions.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: August 15, 2006
    Assignees: Sony Corporation, Sumitomo Electric Industries, Ltd.
    Inventors: Tsunenori Asatsuma, Shigetaka Tomiya, Koshi Tamamura, Tsuyoshi Tojo, Osamu Goto, Kensaku Motoki
  • Publication number: 20050227392
    Abstract: When a semiconductor light emitting device or a semiconductor device is manufactured by growing nitride III-V compound semiconductor layers, which will form a light emitting device structure or a device structure, on a nitride III-V compound semiconductor substrate composed of a first region in form of a crystal having a first average dislocation density and a plurality of second regions having a second average dislocation density higher than the first average dislocation density and periodically aligned in the first region, device regions are defined on the nitride III-V compound semiconductor substrate such that the device regions do not substantially include second regions, emission regions or active regions of devices finally obtained do not include second regions.
    Type: Application
    Filed: June 9, 2005
    Publication date: October 13, 2005
    Inventors: Tsunenori Asatsuma, Shigetaka Tomiya, Koshi Tamamura, Tsuyoshi Tojo, Osamu Goto, Kensaku Motoki
  • Publication number: 20050145879
    Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs. Ordinary one-surface polishing having the steps of gluing a wafer with a surface on a flat disc, bringing another surface in contact with a lower turntable, pressing the disc, rotating the disc, revolving the turntable and whetting the lower surface, cannot remedy the inherent distortion. The Distortion worsens morphology of epitaxial wafers, lowers yield of via-mask exposure and invites cracks on surfaces. Nitride crystals are rigid but fragile. Chemical/mechanical polishing has been requested in vain.
    Type: Application
    Filed: February 11, 2005
    Publication date: July 7, 2005
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SONY CORPORATION
    Inventors: Masahiro Nakayama, Naoki Matsumoto, Koshi Tamamura, Masao Ikeda
  • Patent number: 6875082
    Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs. Ordinary one-surface polishing having the steps of gluing a wafer with a surface on a flat disc, bringing another surface in contact with a lower turntable, pressing the disc, rotating the disc, revolving the turntable and whetting the lower surface, cannot remedy the inherent distortion. The Distortion worsens morphology of epitaxial wafers, lowers yield of via-mask exposure and invites cracks on surfaces. Nitride crystals are rigid but fragile. Chemical/mechanical polishing has been requested in vain.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: April 5, 2005
    Assignees: Sumitomo Electric Industries, Ltd., Sony Corporation
    Inventors: Masahiro Nakayama, Naoki Matsumoto, Koshi Tamamura, Masao Ikeda
  • Publication number: 20040221799
    Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs. Ordinary one-surface polishing having the steps of gluing a wafer with a surface on a flat disc, bringing another surface in contact with a lower turntable, pressing the disc, rotating the disc, revolving the turntable and whetting the lower surface, cannot remedy the inherent distortion. The Distortion worsens morphology of epitaxial wafers, lowers yield of via-mask exposure and invites cracks on surfaces. Nitride crystals are rigid but fragile. Chemical/mechanical polishing has been requested in vain.
    Type: Application
    Filed: September 22, 2003
    Publication date: November 11, 2004
    Applicants: SUMITOMO ELECTRIC INDUSTRIES, LTD., SONY CORPORATION
    Inventors: Masahiro Nakayama, Naoki Matsumoto, Koshi Tamamura, Masao Ikeda
  • Publication number: 20040164308
    Abstract: When a semiconductor light emitting device or a semiconductor device is manufactured by growing nitride III-V compound semiconductor layers, which will form a light emitting device structure or a device structure, on a nitride III-V compound semiconductor substrate composed of a first region in form of a crystal having a first average dislocation density and a plurality of second regions having a second average dislocation density higher than the first average dislocation density and periodically aligned in the first region, device regions are defined on the nitride III-V compound semiconductor substrate such that the device regions do not substantially include second regions, emission regions or active regions of devices finally obtained do not include second regions.
    Type: Application
    Filed: November 21, 2003
    Publication date: August 26, 2004
    Inventors: Tsunenori Asatsuma, Shigetaka Tomiya, Koshi Tamamura, Tsuyoshi Tojo, Osamu Goto, Kensaku Motoki
  • Patent number: 6084251
    Abstract: Disclosed is a semiconductor light emitting device improved in static characteristics such as operational current and prolonged in service life. On an n-type GaAs substrate are sequentially grown an n-type GaAs buffer layer having a thickness of 0.3 .mu.m; an n-type AlGaInP cladding layer having a thickness of 1 .mu.m; and an active layer having a MQW structure of GaInP/AlGaInP. Then, a carrier diffusion suppressing layer having a thickness of 50 nm is grown on the active layer at a reduced V/III ratio. On the carrier diffusion suppressing layer are sequentially grown a p-type AlGaInP cladding layer having a thickness of 1 .mu.m; a p-type GaInP layer having a thickness of 0.1 .mu.m; and a p-type GaAs current cap layer having a thickness of 0.3 .mu.m.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: July 4, 2000
    Assignee: Sony Corporation
    Inventors: Koshi Tamamura, Takayuki Kawasumi, Shoji Hirata
  • Patent number: 6024794
    Abstract: By applying the method, the critical film thickness of a compound semiconductor layer is determined, and a semiconductor device having a compound semiconductor layer with an optimized film thickness excellent in emitting performance is manufactured.The relationship between film thickness of a compound semiconductor layer and photoluminescence (PL) corresponding to the film thickness is obtained by measurement, the film thickness where PL exhibits a peak is designated as critical film thickness. The semiconductor layer comprises II-VI group compound semiconductor layer containing at least cadmium. The relationship between the critical film thickness and cadmium composition ratio is obtained by measurement. An equation which approximates the relationship between the critical film thickness and cadmium composition ratio is formulated.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: February 15, 2000
    Assignee: Sony Corporation
    Inventors: Koshi Tamamura, Hironori Tsukamoto, Masaharu Nagai
  • Patent number: 5989339
    Abstract: A molecular beam epitaxy system having a plurality of chambers which contain at least a first chamber and a second chamber. The first chamber is used to form II-VI column compound semiconductor layers not containing Te. The second chamber is used to form II-VI column compound semiconductor layers containing at least Te. A semiconductor device having an ohmic characteristics can be fabricated without mixing Te into other layers.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: November 23, 1999
    Assignee: Sony Corporation
    Inventors: Koshi Tamamura, Hironori Tsukamoto, Masao Ikeda
  • Patent number: 5949093
    Abstract: A semiconductor light emitting device comprises: a plurality of II-VI compound semiconductor layers stacked on a semiconductor substrate; a contact layer formed on the II-VI compound semiconductor layers; a first first-conduction-type-side electrode and a second first-conduction-type-side electrode formed on the contact layer; and a second-conduction-type-side electrode formed on a bottom surface of the semiconductor substrate, at least a portion of the contact layer underlying the second first-conduction-type-side electrode being changed to a high-resistance region by application of an electric field between the second first-conduction-type-side electrode and the second-conduction-type-side electrode, and the high-resistance region behaving as a current blocking region.
    Type: Grant
    Filed: November 12, 1997
    Date of Patent: September 7, 1999
    Assignee: Sony Corporation
    Inventor: Koshi Tamamura
  • Patent number: 5865897
    Abstract: A film of a II-VI group compound semiconductor of at least one of elements belonging to the II group of the periodic table and at least one of elements belonging to the VI group of the periodic table is deposited on a substrate. When the film is deposited on the substrate, a plasma of nitrogen in an excited state is applied to the substrate while removing charged particles from said plasma by a charged particle removing means. The deposited film of a nitrogen-doped II-VI group compound semiconductor has an increased percentage of activated nitrogen atoms and improved crystallinity.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: February 2, 1999
    Assignee: Sony Corporation
    Inventors: Satoshi Ito, Satoshi Taniguchi, Masao Ikeda, Hiroyuki Okuyama, Hironori Tsukamoto, Masaharu Nagai, Koshi Tamamura
  • Patent number: 5780322
    Abstract: A method for growing a II-VI compound semiconductor layer containing Cd, such as Zn.sub.1-x Cd.sub.x Se, by a molecular beam epitaxy method is disclosed. During the growth, the ratio of the intensity of molecular beams of a group VI element to the intensity of molecular beams of a group II element in terms of intensities of molecular beams actually irradiated onto a substrate, namely, the substantial VI/II ratio, is controlled preferably in the range from 0.7 to 1.3, to increase the Cd incorporating efficiency into the grown layer sufficiently high.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: July 14, 1998
    Assignee: Sony Corporation
    Inventors: Koshi Tamamura, Hironori Tsukamoto, Masao Ikeda