Patents by Inventor Kosuke Hatsuda

Kosuke Hatsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210232326
    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA
  • Patent number: 11074954
    Abstract: According to one embodiment, a memory device includes: a first and a second interconnects; a memory cell including a variable resistive element, the memory cell between the first and second interconnects; and a write circuit including a current source circuit and a voltage source circuit, the write circuit writing data to the memory cell by using a write pulse. The write circuit supplies the write pulse to the memory cell by using the current source circuit in a first period from a first time of a start of supply of the write pulse to a second time, and supplies the write pulse to the memory cell by using the voltage source circuit in a second period from a third time to a fourth time of an end of the supply of the write pulse.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Osada, Kosuke Hatsuda
  • Patent number: 11030043
    Abstract: An error correction circuit includes a syndrome calculator to calculate syndrome information of input data, an error position calculator to calculate error position information of the input data, a holder to hold the syndrome information or the error position information at a predetermined timing, an input switch to select one of error-corrected data of the input data, and the input data, and to input the selected data to the syndrome calculator, an error detection determiner to determine whether an error of the input data has been correctly detected, and an error corrector to correct the error of the input data based on information held by the holder and to output error-corrected input data when it is determined by the error detection determiner that the error has been correctly detected whereas to output the input data with no error correction when it is determined by the error detection determiner.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kosuke Hatsuda
  • Patent number: 10996868
    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 4, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
  • Publication number: 20210103390
    Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.
    Type: Application
    Filed: December 17, 2020
    Publication date: April 8, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Junji YANO, Hidenori MATSUZAKI, Kosuke HATSUDA
  • Publication number: 20210090629
    Abstract: According to one embodiment, a memory device includes first and second wiring lines, a memory cell connected between the first and second wiring lines and including a resistance change memory element and a switching element connected in series to the resistance change memory element, and a determination circuit determining a determination object resistance state set in advance to the resistance change memory element based on a determination object voltage applied to the second wiring line when the switching element makes a transition from an on-state to an off-state.
    Type: Application
    Filed: March 17, 2020
    Publication date: March 25, 2021
    Applicant: KIOXIA CORPORATION
    Inventor: Kosuke HATSUDA
  • Patent number: 10956092
    Abstract: A semiconductor storage device comprises first and second memory cells each including a variable-resistance element, a write driver, and a control circuit that concurrently performs an operation to read first data in the first memory cell and second data in the second memory cell, the operation to read the first data including a first write operation for a first time length and the operation to read the second data including a second write operation for a second time length. In the first write operation, the write driver applies, to the first memory cell, a first voltage for a third time length and a second voltage different from the first voltage for a fourth time length. In the second write operation, the write driver applies the first voltage to the second memory cell for a fifth time length longer than the third time length and longer than the fourth time length.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 23, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Yorinobu Fujino, Kosuke Hatsuda
  • Patent number: 10901625
    Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: January 26, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
  • Publication number: 20200364002
    Abstract: A semiconductor storage device comprises first and second memory cells each including a variable-resistance element, a write driver, and a control circuit that concurrently performs an operation to read first data in the first memory cell and second data in the second memory cell, the operation to read the first data including a first write operation for a first time length and the operation to read the second data including a second write operation for a second time length. In the first write operation, the write driver applies, to the first memory cell, a first voltage for a third time length and a second voltage different from the first voltage for a fourth time length. In the second write operation, the write driver applies the first voltage to the second memory cell for a fifth time length longer than the third time length and longer than the fourth time length.
    Type: Application
    Filed: February 26, 2020
    Publication date: November 19, 2020
    Inventors: Yorinobu FUJINO, Kosuke HATSUDA
  • Publication number: 20200302989
    Abstract: According to one embodiment, a memory device includes: a first and a second interconnects; a memory cell including a variable resistive element, the memory cell between the first and second interconnects; and a write circuit including a current source circuit and a voltage source circuit, the write circuit writing data to the memory cell by using a write pulse. The write circuit supplies the write pulse to the memory cell by using the current source circuit in a first period from a first time of a start of supply of the write pulse to a second time, and supplies the write pulse to the memory cell by using the voltage source circuit in a second period from a third time to a fourth time of an end of the supply of the write pulse.
    Type: Application
    Filed: September 10, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki OSADA, Kosuke HATSUDA
  • Publication number: 20200293403
    Abstract: An error correction circuit includes a syndrome calculator to calculate syndrome information of input data, an error position calculator to calculate error position information of the input data, a holder to hold the syndrome information or the error position information at a predetermined timing, an input switch to select one of error-corrected data of the input data, and the input data, and to input the selected data to the syndrome calculator, an error detection determiner to determine whether an error of the input data has been correctly detected, and an error corrector to correct the error of the input data based on information held by the holder and to output error-corrected input data when it is determined by the error detection determiner that the error has been correctly detected whereas to output the input data with no error correction when it is determined by the error detection determiner.
    Type: Application
    Filed: September 12, 2019
    Publication date: September 17, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Kosuke Hatsuda
  • Patent number: 10535391
    Abstract: According to one embodiment, a semiconductor storage device includes: a first conductor coupled to a first end of a first cell; a second conductor which couples between a second end of the first cell and a first end of a second cell; a third conductor coupled to a second end of the second cell; a first current source being capable of coupling to the first cell via the first conductor; a second current source being capable of coupling to the second cell via the third conductor; a first sense amplifier configured to read data from the first cell based on a current flowing from the first current source to the first cell; and a second sense amplifier configured to read data from the second cell based on a current flowing from the second cell to the second current source.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: January 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Osada, Kosuke Hatsuda
  • Publication number: 20190347016
    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.
    Type: Application
    Filed: July 23, 2019
    Publication date: November 14, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Junji YANO, Hidenori Matsuzaki, Kosuke Hatsuda
  • Patent number: 10431277
    Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data is written and generate a second voltage, and determine data stored in the memory cell at the time of the first read based on the first voltage and the second voltage, wherein when writing the first data, the first circuit electrically sets a generation unit configured to generate the second voltage in a floating state.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: October 1, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kosuke Hatsuda, Yorinobu Fujino
  • Publication number: 20190287594
    Abstract: According to one embodiment, a semiconductor storage device includes: a first conductor coupled to a first end of a first cell; a second conductor which couples between a second end of the first cell and a first end of a second cell; a third conductor coupled to a second end of the second cell; a first current source being capable of coupling to the first cell via the first conductor; a second current source being capable of coupling to the second cell via the third conductor; a first sense amplifier configured to read data from the first cell based on a current flowing from the first current source to the first cell; and a second sense amplifier configured to read data from the second cell based on a current flowing from the second cell to the second current source.
    Type: Application
    Filed: September 6, 2018
    Publication date: September 19, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki OSADA, Kosuke HATSUDA
  • Patent number: 10410733
    Abstract: According to one embodiment, a memory device includes: a memory cell array including a first and a second array; a fuse circuit to hold first data; and a control circuit to control a replacement process on the first and second arrays based on the first data. When a first address in a first direction in the first array is supplied, the fuse circuit transfers the first data corresponding to the first address to the control circuit, and when a second address in a second direction in the first array is supplied after the first data is transferred, the control circuit accesses one of the first and second arrays based on a comparison result for the second address and the first data.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kosuke Hatsuda
  • Patent number: 10388345
    Abstract: According to one embodiment, a memory device includes a preamplifier configured to execute a first read in which a first current relating to a memory cell is passed through a first path and a second current relating to the first current is passed through a second path, to generate a first voltage, to write first data to the memory cell; and to execute a second read in which a third current relating to the memory cell with the first data written thereto is passed through the first path and a fourth current relating to the third current is passed through the second path, to generate a second voltage; and a sense amplifier configured to determine data stored in the memory cell during execution of the first read based on the first voltage and the second voltage.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 20, 2019
    Assignee: TOSHIBA MEMORY CORORATION
    Inventors: Kosuke Hatsuda, Yoshiaki Osada, Yorinobu Fujino, Jieyun Zhou
  • Patent number: 10379762
    Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 13, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
  • Patent number: 10338835
    Abstract: According to one embodiment, a memory device includes a memory cell; a first circuit that performs a first read on the memory cell, writes first data in the memory cell on which the first read has been performed, performs a second read on the memory cell in which the first data has been written, determines data from a result of the first read based on a result of the second read, and writes back the determined data into the memory cell; and an error correcting circuit that performs error correction on the determined data.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: July 2, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Osada, Katsuhiko Hoya, Yorinobu Fujino, Kosuke Hatsuda
  • Patent number: RE47946
    Abstract: To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used. The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: April 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasushi Nagadomi, Daisaburo Takashima, Kosuke Hatsuda, Shinichi Kanno