Abstract: According to one embodiment, a semiconductor storage device includes a memory cell, a bit line connected to the memory cell, and a sense circuit connected to the bit line, wherein the sense circuit includes a first transistor with a first end connected to the bit line, a second transistor with a first end connected to a second end of the first transistor, a third transistor with a first end connected to the bit line, a fourth transistor with a first end connected to a second end of the third transistor, and an amplifier connected to a second end of the second transistor and to a second end of the fourth transistor.

Abstract: According to one embodiment, a semiconductor memory device comprises a first memory cell including a first resistance change element; and a write circuit configured to write data to the first memory cell. The write circuit includes a first circuit including a first input terminal supplied with a first signal based on read data from the first memory cell and a second input terminal supplied with a second signal based on write data to the first memory cell; and a second circuit including a first input terminal supplied with a third signal from an output terminal of the first circuit and a second input terminal supplied with a fourth signal.

Abstract: According to one embodiment, a memory device includes a preamplifier configured to execute a first read in which a first current relating to a memory cell is passed through a first path and a second current relating to the first current is passed through a second path, to generate a first voltage, to write first data to the memory cell; and to execute a second read in which a third current relating to the memory cell with the first data written thereto is passed through the first path and a fourth current relating to the third current is passed through the second path, to generate a second voltage; and a sense amplifier configured to determine data stored in the memory cell during execution of the first read based on the first voltage and the second voltage.

Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.

Abstract: A syndrome calculation circuit receives input data r(x) including data and a parity bit and having a code length n of (2m?1) bits at maximum which is represented by a Galois field GF(2m), and performs syndrome calculation so as to meet s??i+?j z?(?i+?)?1+??1+(?j+?)?1+?1??(A) thereby calculating syndromes s and z. An error position polynomial coefficient calculation circuit calculates the coefficient of an error position polynomial to obtain s×z by multiplying s and z by one multiplier. After that, 2-bit error data positions i and j are specified. Errors at the error data positions i and j of the input data are corrected.

Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data is written and generate a second voltage, and determine data stored in the memory cell at the time of the first read based on the first voltage and the second voltage, wherein when writing the first data, the first circuit electrically sets a generation unit configured to generate the second voltage in a floating state.

Abstract: According to one embodiment, a memory device includes a memory cell; and a first circuit configured to perform first read for the memory cell and generate a first voltage, write first data to the memory cell that has undergone the first read, perform second read for the memory cell to which the first data written and generate a second voltage, generate a first current based on the first voltage, generate a second current based on the second voltage, and add a third current to one of the first current and the second current, thereby determining data stored in the memory cell at the time of the first read.

Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

Abstract: According to one embodiment, a memory device includes a memory cell; a first circuit that performs a first read on the memory cell, writes first data in the memory cell on which the first read has been performed, performs a second read on the memory cell in which the first data has been written, determines data from a result of the first read based on a result of the second read, and writes back the determined data into the memory cell; and an error correcting circuit that performs error correction on the determined data.

Abstract: According to one embodiment, a semiconductor apparatus includes a block and a controller. The block includes a logic circuit and a routing module. The routing module includes a plurality of first wiring lines, a plurality of second wiring lines, switches, and a wiring line switching circuit. The switches are arranged to perform connection and disconnection between the first wiring lines and the second wiring lines. The wiring line switching circuit is arranged to switch a wiring line for transmitting the signal, among the first wiring lines and the second wiring lines. The controller is arranged to control driving of the switches and the wiring line switching circuit.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell, a bit line connected to the memory cell, and a sense circuit connected to the bit line, wherein the sense circuit includes a first transistor with a first end connected to the bit line, a second transistor with a first end connected to a second end of the first transistor, a third transistor with a first end connected to the bit line, a fourth transistor with a first end connected to a second end of the third transistor, and an amplifier connected to a second end of the second transistor and to a second end of the fourth transistor.

Abstract: According to one embodiment, a memory device includes: a memory cell array including a first and a second array; a fuse circuit to hold first data; and a control circuit to control a replacement process on the first and second arrays based on the first data. When a first address in a first direction in the first array is supplied, the fuse circuit transfers the first data corresponding to the first address to the control circuit, and when a second address in a second direction in the first array is supplied after the first data is transferred, the control circuit accesses one of the first and second arrays based on a comparison result for the second address and the first data.

Abstract: According to one embodiment, a semiconductor memory device includes: a first bit line; a first source line; a first word line; a first control line; a first memory cell comprising a first variable resistance element and a first transistor, the first transistor including a gate coupled to the first word line, the first memory cell including one end coupled to the first bit line and another end coupled to the first source line; a second transistor including one end coupled to the first bit line; and a third transistor including a gate coupled to the first control line, one end coupled to the first bit line, and another end coupled to the first source line.

Abstract: According to one embodiment, a semiconductor memory device includes: a first bit line; a first source line; a first word line; a first control line; a first memory cell comprising a first variable resistance element and a first transistor, the first transistor including a gate coupled to the first word line, the first memory cell including one end coupled to the first bit line and another end coupled to the first source line; a second transistor including one end coupled to the first bit line; and a third transistor including a gate coupled to the first control line, one end coupled to the first bit line, and another and coupled to the first source line.

Abstract: A syndrome calculation circuit receives input data r(x) including data and a parity bit and having a code length n of (2m-1) bits at maximum which is represented by a Galois field GF(2m), and performs syndrome calculation so as to meet s??i+?j z?(?i+?)?1+??1+(?j+?)?1+?1 ??(A) thereby calculating syndromes s and z. An error position polynomial coefficient calculation circuit calculates the coefficient of an error position polynomial to obtain s×z by multiplying s and z by one multiplier. After that, 2-bit error data positions i and j are specified. Errors at the error data positions i and j of the input data are corrected.

Abstract: According to one embodiment, a semiconductor apparatus includes a block and a controller. The block includes a logic circuit and a routing module. The routing module includes a plurality of first wiring lines, a plurality of second wiring lines, switches, and a wiring line switching circuit. The switches are arranged to perform connection and disconnection between the first wiring lines and the second wiring lines. The wiring line switching circuit is arranged to switch a wiring line for transmitting the signal, among the first wiring lines and the second wiring lines. The controller is arranged to control driving of the switches and the wiring line switching circuit.

Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

Abstract: A first normal bit and source lines are connected to a first memory cell. Second normal bit and source lines are connected to a second memory cell. A first column switch connects one of the first and second normal bit lines to a first global bit line. A second column switch connects one of the first and second normal source lines to a first global source line. A first reference bit and source lines are connected to a third memory cell. A third column switch connects the first reference bit line to a second global bit line. A fourth column switch connects the first reference source line to the first global source line. A sense amplifier is connected to the first and second global bit lines, and reads data stored in one of the first and second memory cells.