Patents by Inventor Kota Hara

Kota Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240117393
    Abstract: A method for producing an L-amino acid such as L-glutamic acid is provided. An L-amino acid is produced by culturing in a culture medium a bacterium belonging to the family Enterobacteriaceae and having an L-amino acid-producing ability, and collecting the L-amino acid from the culture medium and/or cells of the bacterium, wherein the bacterium has been modified to have one or more of the following modifications: (A) modification of reducing the activity of a BudA protein; (B) modification of reducing the activity of a BudB protein; (C) modification of reducing the activity of a BudC protein; (D) modification of reducing the activity of a PAJ_3461 protein; (E) modification of reducing the activity of a PAJ_3462 protein; and (F) modification of reducing the activity of a PAJ_3463 protein.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 11, 2024
    Applicant: AJINOMOTO CO., INC.
    Inventors: Chie HAMANO, Yoshihiro ITO, Naoki EBARA, Kota INOUE, Yukiko ONO, Rihito ISHIDA, Fumito ONISHI, Yoshihiko HARA
  • Publication number: 20210406960
    Abstract: For an input image of a person, a set of object proposals are generated in the form of bounding boxes. A pose detector identifies coordinates in the image corresponding to locations on the person's body, such as the waist, head, hands, and feet of the person. A convolutional neural network receives the portions of the input image defined by the bounding boxes and generates a feature vector for each image portion. The feature vectors are input to one or more support vector machine classifiers, which generate an output representing a probability of a match with an item. The distance between the bounding box and a joint associated with the item is used to modify the probability. The modified probabilities for the support vector machine are then compared with a threshold and each other to identify the item.
    Type: Application
    Filed: September 13, 2021
    Publication date: December 30, 2021
    Applicant: eBay Inc.
    Inventors: Kota Hara, Vignesh Jagadeesh, Robinson Piramuthu
  • Patent number: 11120478
    Abstract: For an input image of a person, a set of object proposals are generated in the form of bounding boxes. A pose detector identifies coordinates in the image corresponding to locations on the person's body, such as the waist, head, hands, and feet of the person. A convolutional neural network receives the portions of the input image defined by the bounding boxes and generates a feature vector for each image portion. The feature vectors are input to one or more support vector machine classifiers, which generate an output representing a probability of a match with an item. The distance between the bounding box and a joint associated with the item is used to modify the probability. The modified probabilities for the support vector machine are then compared with a threshold and each other to identify the item.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: September 14, 2021
    Assignee: eBay Inc.
    Inventors: Kota Hara, Vignesh Jagadeesh, Robinson Piramuthu
  • Patent number: 10210418
    Abstract: A method detects an object in an image. The method extracts a first feature vector from a first region of an image using a first subnetwork and determines a second region of the image by processing the first feature vector with a second subnetwork. The method also extracts a second feature vector from the second region of the image using the first subnetwork and detects the object using a third subnetwork on a basis of the first feature vector and the second feature vector to produce a bounding region surrounding the object and a class of the object. The first subnetwork, the second subnetwork, and the third subnetwork form a neural network. Also, a size of the first region differs from a size of the second region.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: February 19, 2019
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Ming-Yu Liu, Oncel Tuzel, Amir massoud Farahmand, Kota Hara
  • Publication number: 20180025249
    Abstract: A method detects an object in an image. The method extracts a first feature vector from a first region of an image using a first subnetwork and determines a second region of the image by processing the first feature vector with a second subnetwork. The method also extracts a second feature vector from the second region of the image using the first subnetwork and detects the object using a third subnetwork on a basis of the first feature vector and the second feature vector to produce a bounding region surrounding the object and a class of the object. The first subnetwork, the second subnetwork, and the third subnetwork form a neural network. Also, a size of the first region differs from a size of the second region.
    Type: Application
    Filed: July 25, 2016
    Publication date: January 25, 2018
    Applicant: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Ming-Yu Liu, Oncel Tuzel, Amir massoud Farahmand, Kota Hara
  • Publication number: 20160203525
    Abstract: For an input image of a person, a set of object proposals are generated in the form of bounding boxes. A pose detector identifies coordinates in the image corresponding to locations on the person's body, such as the waist, head, hands, and feet of the person. A convolutional neural network receives the portions of the input image defined by the bounding boxes and generates a feature vector for each image portion. The feature vectors are input to one or more support vector machine classifiers, which generate an output representing a probability of a match with an item. The distance between the bounding box and a joint associated with the item is used to modify the probability. The modified probabilities for the support vector machine are then compared with a threshold and each other to identify the item.
    Type: Application
    Filed: December 8, 2015
    Publication date: July 14, 2016
    Inventors: Kota Hara, Vignesh Jagadeesh, Robinson Piramuthu
  • Patent number: 8724425
    Abstract: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: May 13, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kota Hara
  • Patent number: 8274854
    Abstract: A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 25, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kota Hara
  • Publication number: 20120147691
    Abstract: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.
    Type: Application
    Filed: February 16, 2012
    Publication date: June 14, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Kota HARA
  • Publication number: 20120087195
    Abstract: A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.
    Type: Application
    Filed: December 19, 2011
    Publication date: April 12, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Kota HARA
  • Patent number: 8139438
    Abstract: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: March 20, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kota Hara
  • Patent number: 8107314
    Abstract: A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: January 31, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kota Hara
  • Patent number: 8098531
    Abstract: In a semiconductor memory device which uses a same pad for an address input and data input/output, and has an input circuit and data output circuit connected to the pad, an output of the data output circuit is turned to a high impedance state in accordance with a chip enable signal, output enable signal, and address capture signal, at a stand-by time, output disable time, and address capture period, and thereby, it becomes possible to start an internal read operation even before the address capture period is finished, and a high-speed operation becomes possible.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: January 17, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kota Hara, Katsuhiro Mori
  • Patent number: 7697367
    Abstract: A semiconductor memory device includes memory blocks, a main word decoder to set a main word line to a first potential for activation, a second potential, or a third potential, a circuit to generate a cyclic signal that indicates timing at intervals, a block selecting circuit to select a memory block to be accessed, a successive-selection circuit to select the memory blocks one after another, and a circuit configured to control the main word decoder such that unselected ones of the main word lines of a memory block selected by the block selecting circuit are set to the third potential, such that the main word lines of the selected memory block are maintained at the third potential after access, and such that the main word lines of a memory block selected by the successive-selection circuit are set to the second potential at the timing indicated by the cyclic signal.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: April 13, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Kota Hara
  • Patent number: 7672181
    Abstract: Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: March 2, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kaoru Mori, Kota Hara, Jun Ohno
  • Publication number: 20090245012
    Abstract: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.
    Type: Application
    Filed: March 26, 2009
    Publication date: October 1, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Kota HARA
  • Publication number: 20090190416
    Abstract: A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 30, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Kota HARA
  • Patent number: 7531485
    Abstract: On producing a lubricant which is used in making a lubrication layer included in a magnetic disk from the lubricant, a phosphorus-containing compound is removed from a raw-material lubricant including the phosphorus-containing compound to produce the lubricant. The magnetic disk includes a substrate on which at least a magnetic layer, a protection layer, and the lubrication layer formed by the use of the lubricant are successively formed.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: May 12, 2009
    Assignee: Hoya Corporation
    Inventors: Kota Hara, Koichi Shimokawa, Kota Suzuki
  • Publication number: 20090092000
    Abstract: A semiconductor memory device includes memory blocks, a main word decoder to set a main word line to a first potential for activation, a second potential, or a third potential, a circuit to generate a cyclic signal that indicates timing at intervals, a block selecting circuit to select a memory block to be accessed, a successive-selection circuit to select the memory blocks one after another, and a circuit configured to control the main word decoder such that unselected ones of the main word lines of a memory block selected by the block selecting circuit are set to the third potential, such that the main word lines of the selected memory block are maintained at the third potential after access, and such that the main word lines of a memory block selected by the successive-selection circuit are set to the second potential at the timing indicated by the cyclic signal.
    Type: Application
    Filed: June 26, 2008
    Publication date: April 9, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Kota Hara
  • Publication number: 20090040851
    Abstract: Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily.
    Type: Application
    Filed: May 30, 2008
    Publication date: February 12, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Kaoru MORI, Kota Hara, Jun Ohno