Patents by Inventor Kota Hara
Kota Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240117393Abstract: A method for producing an L-amino acid such as L-glutamic acid is provided. An L-amino acid is produced by culturing in a culture medium a bacterium belonging to the family Enterobacteriaceae and having an L-amino acid-producing ability, and collecting the L-amino acid from the culture medium and/or cells of the bacterium, wherein the bacterium has been modified to have one or more of the following modifications: (A) modification of reducing the activity of a BudA protein; (B) modification of reducing the activity of a BudB protein; (C) modification of reducing the activity of a BudC protein; (D) modification of reducing the activity of a PAJ_3461 protein; (E) modification of reducing the activity of a PAJ_3462 protein; and (F) modification of reducing the activity of a PAJ_3463 protein.Type: ApplicationFiled: September 26, 2023Publication date: April 11, 2024Applicant: AJINOMOTO CO., INC.Inventors: Chie HAMANO, Yoshihiro ITO, Naoki EBARA, Kota INOUE, Yukiko ONO, Rihito ISHIDA, Fumito ONISHI, Yoshihiko HARA
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Publication number: 20210406960Abstract: For an input image of a person, a set of object proposals are generated in the form of bounding boxes. A pose detector identifies coordinates in the image corresponding to locations on the person's body, such as the waist, head, hands, and feet of the person. A convolutional neural network receives the portions of the input image defined by the bounding boxes and generates a feature vector for each image portion. The feature vectors are input to one or more support vector machine classifiers, which generate an output representing a probability of a match with an item. The distance between the bounding box and a joint associated with the item is used to modify the probability. The modified probabilities for the support vector machine are then compared with a threshold and each other to identify the item.Type: ApplicationFiled: September 13, 2021Publication date: December 30, 2021Applicant: eBay Inc.Inventors: Kota Hara, Vignesh Jagadeesh, Robinson Piramuthu
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Patent number: 11120478Abstract: For an input image of a person, a set of object proposals are generated in the form of bounding boxes. A pose detector identifies coordinates in the image corresponding to locations on the person's body, such as the waist, head, hands, and feet of the person. A convolutional neural network receives the portions of the input image defined by the bounding boxes and generates a feature vector for each image portion. The feature vectors are input to one or more support vector machine classifiers, which generate an output representing a probability of a match with an item. The distance between the bounding box and a joint associated with the item is used to modify the probability. The modified probabilities for the support vector machine are then compared with a threshold and each other to identify the item.Type: GrantFiled: December 8, 2015Date of Patent: September 14, 2021Assignee: eBay Inc.Inventors: Kota Hara, Vignesh Jagadeesh, Robinson Piramuthu
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Patent number: 10210418Abstract: A method detects an object in an image. The method extracts a first feature vector from a first region of an image using a first subnetwork and determines a second region of the image by processing the first feature vector with a second subnetwork. The method also extracts a second feature vector from the second region of the image using the first subnetwork and detects the object using a third subnetwork on a basis of the first feature vector and the second feature vector to produce a bounding region surrounding the object and a class of the object. The first subnetwork, the second subnetwork, and the third subnetwork form a neural network. Also, a size of the first region differs from a size of the second region.Type: GrantFiled: July 25, 2016Date of Patent: February 19, 2019Assignee: Mitsubishi Electric Research Laboratories, Inc.Inventors: Ming-Yu Liu, Oncel Tuzel, Amir massoud Farahmand, Kota Hara
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Publication number: 20180025249Abstract: A method detects an object in an image. The method extracts a first feature vector from a first region of an image using a first subnetwork and determines a second region of the image by processing the first feature vector with a second subnetwork. The method also extracts a second feature vector from the second region of the image using the first subnetwork and detects the object using a third subnetwork on a basis of the first feature vector and the second feature vector to produce a bounding region surrounding the object and a class of the object. The first subnetwork, the second subnetwork, and the third subnetwork form a neural network. Also, a size of the first region differs from a size of the second region.Type: ApplicationFiled: July 25, 2016Publication date: January 25, 2018Applicant: Mitsubishi Electric Research Laboratories, Inc.Inventors: Ming-Yu Liu, Oncel Tuzel, Amir massoud Farahmand, Kota Hara
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Publication number: 20160203525Abstract: For an input image of a person, a set of object proposals are generated in the form of bounding boxes. A pose detector identifies coordinates in the image corresponding to locations on the person's body, such as the waist, head, hands, and feet of the person. A convolutional neural network receives the portions of the input image defined by the bounding boxes and generates a feature vector for each image portion. The feature vectors are input to one or more support vector machine classifiers, which generate an output representing a probability of a match with an item. The distance between the bounding box and a joint associated with the item is used to modify the probability. The modified probabilities for the support vector machine are then compared with a threshold and each other to identify the item.Type: ApplicationFiled: December 8, 2015Publication date: July 14, 2016Inventors: Kota Hara, Vignesh Jagadeesh, Robinson Piramuthu
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Patent number: 8724425Abstract: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.Type: GrantFiled: February 16, 2012Date of Patent: May 13, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Kota Hara
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Patent number: 8274854Abstract: A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.Type: GrantFiled: December 19, 2011Date of Patent: September 25, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Kota Hara
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Publication number: 20120147691Abstract: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.Type: ApplicationFiled: February 16, 2012Publication date: June 14, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Kota HARA
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Publication number: 20120087195Abstract: A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.Type: ApplicationFiled: December 19, 2011Publication date: April 12, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Kota HARA
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Patent number: 8139438Abstract: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.Type: GrantFiled: March 26, 2009Date of Patent: March 20, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Kota Hara
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Patent number: 8107314Abstract: A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.Type: GrantFiled: January 27, 2009Date of Patent: January 31, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Kota Hara
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Patent number: 8098531Abstract: In a semiconductor memory device which uses a same pad for an address input and data input/output, and has an input circuit and data output circuit connected to the pad, an output of the data output circuit is turned to a high impedance state in accordance with a chip enable signal, output enable signal, and address capture signal, at a stand-by time, output disable time, and address capture period, and thereby, it becomes possible to start an internal read operation even before the address capture period is finished, and a high-speed operation becomes possible.Type: GrantFiled: October 18, 2007Date of Patent: January 17, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Kota Hara, Katsuhiro Mori
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Patent number: 7697367Abstract: A semiconductor memory device includes memory blocks, a main word decoder to set a main word line to a first potential for activation, a second potential, or a third potential, a circuit to generate a cyclic signal that indicates timing at intervals, a block selecting circuit to select a memory block to be accessed, a successive-selection circuit to select the memory blocks one after another, and a circuit configured to control the main word decoder such that unselected ones of the main word lines of a memory block selected by the block selecting circuit are set to the third potential, such that the main word lines of the selected memory block are maintained at the third potential after access, and such that the main word lines of a memory block selected by the successive-selection circuit are set to the second potential at the timing indicated by the cyclic signal.Type: GrantFiled: June 26, 2008Date of Patent: April 13, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Kota Hara
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Patent number: 7672181Abstract: Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily.Type: GrantFiled: May 30, 2008Date of Patent: March 2, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Kaoru Mori, Kota Hara, Jun Ohno
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Publication number: 20090245012Abstract: A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal.Type: ApplicationFiled: March 26, 2009Publication date: October 1, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Kota HARA
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Publication number: 20090190416Abstract: A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode.Type: ApplicationFiled: January 27, 2009Publication date: July 30, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Kota HARA
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Patent number: 7531485Abstract: On producing a lubricant which is used in making a lubrication layer included in a magnetic disk from the lubricant, a phosphorus-containing compound is removed from a raw-material lubricant including the phosphorus-containing compound to produce the lubricant. The magnetic disk includes a substrate on which at least a magnetic layer, a protection layer, and the lubrication layer formed by the use of the lubricant are successively formed.Type: GrantFiled: September 26, 2005Date of Patent: May 12, 2009Assignee: Hoya CorporationInventors: Kota Hara, Koichi Shimokawa, Kota Suzuki
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Publication number: 20090092000Abstract: A semiconductor memory device includes memory blocks, a main word decoder to set a main word line to a first potential for activation, a second potential, or a third potential, a circuit to generate a cyclic signal that indicates timing at intervals, a block selecting circuit to select a memory block to be accessed, a successive-selection circuit to select the memory blocks one after another, and a circuit configured to control the main word decoder such that unselected ones of the main word lines of a memory block selected by the block selecting circuit are set to the third potential, such that the main word lines of the selected memory block are maintained at the third potential after access, and such that the main word lines of a memory block selected by the successive-selection circuit are set to the second potential at the timing indicated by the cyclic signal.Type: ApplicationFiled: June 26, 2008Publication date: April 9, 2009Applicant: FUJITSU LIMITEDInventor: Kota Hara
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Publication number: 20090040851Abstract: Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily.Type: ApplicationFiled: May 30, 2008Publication date: February 12, 2009Applicant: FUJITSU LIMITEDInventors: Kaoru MORI, Kota Hara, Jun Ohno